公开(公告)号：US08181003B2

公开(公告)日：2012-05-15

申请号：US12156007

申请日：2008-05-29

申请人： Xiaolin Wang ,  Qian Wu ,  Benjamin Marshall ,  Fugui Wang ,  Gregory Pitarys ,  Ke Ning

发明人： Xiaolin Wang ,  Qian Wu ,  Benjamin Marshall ,  Fugui Wang ,  Gregory Pitarys ,  Ke Ning

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/30181 ,  G06F9/3867 ,  G06F9/3885 ,  G06F9/3897

摘要： Improved instruction set and core design, control and communication for programmable microprocessors is disclosed, involving the strategy for replacing centralized program sequencing in present-day and prior art processors with a novel distributed program sequencing wherein each functional unit has its own instruction fetch and decode block, and each functional unit has its own local memory for program storage; and wherein computational hardware execution units and memory units are flexibly pipelined as programmable embedded processors with reconfigurable pipeline stages of different order in response to varying application instruction sequences that establish different configurations and switching interconnections of the hardware units.

摘要翻译： 公开了针对可编程微处理器的改进的指令集和核心设计，控制和通信，其涉及用新的分布式程序排序代替当前和现有技术处理器中的集中程序排序的策略，其中每个功能单元具有其自己的指令获取和解码块 ，并且每个功能单元具有其自己的用于程序存储的本地存储器; 并且其中响应于建立硬件单元的不同配置和切换互连的变化的应用指令序列，计算硬件执行单元和存储器单元被灵活地流水线化为具有不同顺序的可重新配置流水线级的可编程嵌入式处理器。

公开(公告)号：US20090300337A1

公开(公告)日：2009-12-03

申请号：US12156007

申请日：2008-05-29

申请人： Xiaolin Wang ,  Qian Wu ,  Benjamin Marshall ,  Fugui Wang ,  Gregory Pitarys ,  Ke Ning

发明人： Xiaolin Wang ,  Qian Wu ,  Benjamin Marshall ,  Fugui Wang ,  Gregory Pitarys ,  Ke Ning

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/30181 ,  G06F9/3867 ,  G06F9/3885 ,  G06F9/3897

摘要： Improved instruction set and core design, control and communication for programmable microprocessors is disclosed, involving the strategy for replacing centralized program sequencing in present-day and prior art processors with a novel distributed program sequencing wherein each functional unit has its own instruction fetch and decode block, and each functional unit has its own local memory for program storage; and wherein computational hardware execution units and memory units are flexibly pipelined as programmable embedded processors with reconfigurable pipeline stages of different order in response to varying application instruction sequences that establish different configurations and switching interconnections of the hardware units.

摘要翻译： 公开了针对可编程微处理器的改进的指令集和核心设计，控制和通信，其涉及用新的分布式程序排序代替当前和现有技术处理器中的集中程序排序的策略，其中每个功能单元具有其自己的指令获取和解码块 ，并且每个功能单元具有其自己的用于程序存储的本地存储器; 并且其中响应于建立硬件单元的不同配置和切换互连的变化的应用指令序列，计算硬件执行单元和存储器单元被灵活地流水线化为具有不同顺序的可重新配置流水线级的可编程嵌入式处理器。

公开(公告)号：US08078833B2

公开(公告)日：2011-12-13

申请号：US12156006

申请日：2008-05-29

申请人： Xiaolin Wang ,  Qian Wu ,  Benjamin Marshall ,  Fugui Wang ,  Ke Ning ,  Gregory Pitarys

发明人： Xiaolin Wang ,  Qian Wu ,  Benjamin Marshall ,  Fugui Wang ,  Ke Ning ,  Gregory Pitarys

IPC分类号： G06F15/00 ,  G06F15/76

CPC分类号： G06F5/015 ,  G06F9/30014 ,  G06F9/30181 ,  G06F9/3873 ,  G06F9/3875 ,  G06F9/3897

摘要： The invention resides in a flexible data pipeline structure for accommodating software computational instructions for varying application programs and having a programmable embedded processor with internal pipeline stages the order and length of which varies as fast as every clock cycle based on the instruction sequence in an application program preloaded into the processor, and wherein the processor includes a data switch matrix selectively and flexibly interconnecting pluralities of mathematical execution units and memory units in response to said instructions, and wherein the execution units are configurable to perform operations at different precisions of multi-bit arithmetic and logic operations and in a multi-level hierarchical architecture structure.

摘要翻译： 本发明涉及一种灵活的数据流水线结构，用于容纳用于变化的应用程序的软件计算指令，并且具有可编程嵌入式处理器，其具有内部流水线阶段，其顺序和长度基于应用程序中的指令序列而变化为每个时钟周期快 并且其中所述处理器包括数据交换矩阵，所述数据交换矩阵响应于所述指令选择性地和灵活地互连多个数学执行单元和存储器单元，并且其中所述执行单元可配置为以不同精度执行多位运算 逻辑运算和多级分层结构。

公开(公告)号：US20090300336A1

公开(公告)日：2009-12-03

申请号：US12156006

申请日：2008-05-29

申请人： Xiaolin Wang ,  Qian Wu ,  Benjamin Marshall ,  Fugui Wang ,  Ke Ning ,  Gregory Pitarys

发明人： Xiaolin Wang ,  Qian Wu ,  Benjamin Marshall ,  Fugui Wang ,  Ke Ning ,  Gregory Pitarys

IPC分类号： G06F9/302

CPC分类号： G06F5/015 ,  G06F9/30014 ,  G06F9/30181 ,  G06F9/3873 ,  G06F9/3875 ,  G06F9/3897

摘要： The invention resides in a flexible data pipeline structure for accommodating software computational instructions for varying application programs and having a programmable embedded processor with internal pipeline stages the order and length of which varies as fast as every clock cycle based on the instruction sequence in an application program preloaded into the processor, and wherein the processor includes a data switch matrix selectively and flexibly interconnecting pluralities of mathematical execution units and memory units in response to said instructions, and wherein the execution units are configurable to perform operations at different precisions of multi-bit arithmetic and logic operations and in a multi-level hierarchical architecture structure.

摘要翻译： 本发明涉及一种灵活的数据流水线结构，用于容纳用于变化的应用程序的软件计算指令，并且具有可编程嵌入式处理器，其具有内部流水线阶段，其顺序和长度基于应用程序中的指令序列而变化为每个时钟周期快 并且其中所述处理器包括数据交换矩阵，所述数据交换矩阵响应于所述指令选择性地和灵活地互连多个数学执行单元和存储器单元，并且其中所述执行单元可配置为以不同精度执行多位运算 逻辑运算和多级分层结构。

公开(公告)号：US10140124B2

公开(公告)日：2018-11-27

申请号：US15876696

申请日：2018-01-22

申请人： Xiaolin Wang ,  Qian Wu

发明人： Xiaolin Wang ,  Qian Wu

IPC分类号： G06F9/4401 ,  G06F9/30 ,  H04B1/00 ,  G06F15/78 ,  G06F17/50 ,  G06F9/455 ,  G06F15/76

摘要： A reconfigurable, multi-core processor includes a plurality of memory blocks and programmable elements, including units for processing, memory interface, and on-chip cognitive data routing, all interconnected by a self-routing cognitive on-chip network. In embodiments, the processing units perform intrinsic operations in any order, and the self-routing network forms interconnections that allow the sequence of operations to be varied and both synchronous and asynchronous data to be transmitted as needed. A method for programming the processor includes partitioning an application into modules, determining whether the modules execute in series, program-driven parallel, or data-driven parallel, determining the data flow required between the modules, assigning hardware resources as needed, and automatically generating machine code for each module. In embodiments, a Time Field is added to the instruction format for all programming units that specifies the number of clock cycles for which only one instruction fetch and decode will be performed.

公开(公告)号：US20190056941A1

公开(公告)日：2019-02-21

申请号：US16168088

申请日：2018-10-23

申请人： Xiaolin Wang ,  Qian Wu

发明人： Xiaolin Wang ,  Qian Wu

IPC分类号： G06F9/30 ,  H04B1/00 ,  G06F17/50 ,  G06F9/455 ,  G06F15/78 ,  G06F15/76

CPC分类号： G06F9/30181 ,  G06F9/455 ,  G06F15/76 ,  G06F15/7867 ,  G06F17/5054 ,  G06F2015/768 ,  H04B1/0003

摘要： A reconfigurable, multi-core processor includes a plurality of memory blocks and programmable elements, including units for processing, memory interface, and on-chip cognitive data routing, all interconnected by a self-routing cognitive on-chip network. In embodiments, the processing units perform intrinsic operations in any order, and the self-routing network forms interconnections that allow the sequence of operations to be varied and both synchronous and asynchronous data to be transmitted as needed. A method for programming the processor includes partitioning an application into modules, determining whether the modules execute in series, program-driven parallel, or data-driven parallel, determining the data flow required between the modules, assigning hardware resources as needed, and automatically generating machine code for each module. In embodiments, Time Fields are added to the instruction format for all programming units that specify the number of clock cycles for which only one fetched and decoded instruction will be executed.

公开(公告)号：US20180143834A1

公开(公告)日：2018-05-24

申请号：US15876696

申请日：2018-01-22

申请人： Xiaolin Wang ,  Qian Wu

发明人： Xiaolin Wang ,  Qian Wu

IPC分类号： G06F9/30 ,  H04B1/00 ,  G06F17/50 ,  G06F9/455 ,  G06F15/78 ,  G06F15/76

CPC分类号： G06F9/30181 ,  G06F9/455 ,  G06F15/76 ,  G06F15/7867 ,  G06F17/5054 ,  G06F2015/768 ,  H04B1/0003

摘要： A reconfigurable, multi-core processor includes a plurality of memory blocks and programmable elements, including units for processing, memory interface, and on-chip cognitive data routing, all interconnected by a self-routing cognitive on-chip network. In embodiments, the processing units perform intrinsic operations in any order, and the self-routing network forms interconnections that allow the sequence of operations to be varied and both synchronous and asynchronous data to be transmitted as needed. A method for programming the processor includes partitioning an application into modules, determining whether the modules execute in series, program-driven parallel, or data-driven parallel, determining the data flow required between the modules, assigning hardware resources as needed, and automatically generating machine code for each module. In embodiments, a Time Field is added to the instruction format for all programming units that specifies the number of clock cycles for which only one instruction fetch and decode will be performed.

公开(公告)号：US20130044634A1

公开(公告)日：2013-02-21

申请号：US13588012

申请日：2012-08-17

申请人： Xiaolin Wang ,  Qian Wu ,  Jie Sun

发明人： Xiaolin Wang ,  Qian Wu ,  Jie Sun

IPC分类号： H04L12/66

CPC分类号： H04L12/6418

摘要： A dynamically reconfigurable network architecture includes a plurality of switching modules arranged in an ordered, multi-level, switched-tree configuration. A network is formed by selecting one switching module as the root and assigning it and all directly or indirectly subsidiary modules to the network. The operating mode of each switching module can be dynamically selected as either circuit-switched or packet-switched. The modules can be grouped into a single network or into a plurality of separate networks operating in parallel, including both circuit-switched and packet-switched networks. When a network is no longer needed, its operation can be halted and its resources released for reassignment to other networks. In embodiments, a selector controlled by allocation registers selects either a circuit-switching sequencer or a packet connection arbitration circuit to control the switching circuits. Switching modules can include crossbar switches. Circuit-switched connections can use TDM to share allocated physical resources.

摘要翻译： 动态可重新配置的网络架构包括以有序，多层次的交换树配置布置的多个交换模块。 通过选择一个交换模块作为根，并将其分配到所有直接或间接的辅助模块来形成网络。 每个切换模块的操作模式可以被动态地选择为电路交换或分组交换。 这些模块可以被分组成单个网络或者并行操作的多个独立网络，包括电路交换网络和分组交换网络。 当不再需要网络时，可以停止其操作并释放其资源以重新分配给其他网络。 在实施例中，由分配寄存器控制的选择器选择电路切换定序器或分组连接仲裁电路来控制开关电路。 交换模块可以包括交叉开关。 电路交换连接可以使用TDM来共享所分配的物理资源。

公开(公告)号：US08811387B2

公开(公告)日：2014-08-19

申请号：US13588012

申请日：2012-08-17

申请人： Xiaolin Wang ,  Qian Wu ,  Jie Sun

发明人： Xiaolin Wang ,  Qian Wu ,  Jie Sun

IPC分类号： H04L12/66 ,  H04Q11/00 ,  H04L12/28

CPC分类号： H04L12/6418

摘要： A dynamically reconfigurable network architecture includes a plurality of switching modules arranged in an ordered, multi-level, switched-tree configuration. A network is formed by selecting one switching module as the root and assigning it and all directly or indirectly subsidiary modules to the network. The operating mode of each switching module can be dynamically selected as either circuit-switched or packet-switched. The modules can be grouped into a single network or into a plurality of separate networks operating in parallel, including both circuit-switched and packet-switched networks. When a network is no longer needed, its operation can be halted and its resources released for reassignment to other networks. In embodiments, a selector controlled by allocation registers selects either a circuit-switching sequencer or a packet connection arbitration circuit to control the switching circuits. Switching modules can include crossbar switches. Circuit-switched connections can use TDM to share allocated physical resources.

摘要翻译： 动态可重新配置的网络架构包括以有序，多层次的交换树配置布置的多个交换模块。 通过选择一个交换模块作为根，并将其分配到所有直接或间接的辅助模块来形成网络。 每个切换模块的操作模式可以被动态地选择为电路交换或分组交换。 这些模块可以被分组成单个网络或者并行操作的多个独立网络，包括电路交换网络和分组交换网络。 当不再需要网络时，可以停止其操作并释放其资源以重新分配给其他网络。 在实施例中，由分配寄存器控制的选择器选择电路切换定序器或分组连接仲裁电路来控制开关电路。 交换模块可以包括交叉开关。 电路交换连接可以使用TDM来共享所分配的物理资源。

公开(公告)号：US10445099B2

公开(公告)日：2019-10-15

申请号：US16168088

申请日：2018-10-23

申请人： Xiaolin Wang ,  Qian Wu

发明人： Xiaolin Wang ,  Qian Wu

IPC分类号： G06F9/30 ,  G06F15/78 ,  G06F15/76 ,  G06F17/50 ,  H04B1/00 ,  G06F9/455

摘要： A reconfigurable, multi-core processor includes a plurality of memory blocks and programmable elements, including units for processing, memory interface, and on-chip cognitive data routing, all interconnected by a self-routing cognitive on-chip network. In embodiments, the processing units perform intrinsic operations in any order, and the self-routing network forms interconnections that allow the sequence of operations to be varied and both synchronous and asynchronous data to be transmitted as needed. A method for programming the processor includes partitioning an application into modules, determining whether the modules execute in series, program-driven parallel, or data-driven parallel, determining the data flow required between the modules, assigning hardware resources as needed, and automatically generating machine code for each module. In embodiments, Time Fields are added to the instruction format for all programming units that specify the number of clock cycles for which only one fetched and decoded instruction will be executed.