公开(公告)号：US08181003B2

公开(公告)日：2012-05-15

申请号：US12156007

申请日：2008-05-29

申请人： Xiaolin Wang ,  Qian Wu ,  Benjamin Marshall ,  Fugui Wang ,  Gregory Pitarys ,  Ke Ning

发明人： Xiaolin Wang ,  Qian Wu ,  Benjamin Marshall ,  Fugui Wang ,  Gregory Pitarys ,  Ke Ning

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/30181 ,  G06F9/3867 ,  G06F9/3885 ,  G06F9/3897

摘要： Improved instruction set and core design, control and communication for programmable microprocessors is disclosed, involving the strategy for replacing centralized program sequencing in present-day and prior art processors with a novel distributed program sequencing wherein each functional unit has its own instruction fetch and decode block, and each functional unit has its own local memory for program storage; and wherein computational hardware execution units and memory units are flexibly pipelined as programmable embedded processors with reconfigurable pipeline stages of different order in response to varying application instruction sequences that establish different configurations and switching interconnections of the hardware units.

摘要翻译： 公开了针对可编程微处理器的改进的指令集和核心设计，控制和通信，其涉及用新的分布式程序排序代替当前和现有技术处理器中的集中程序排序的策略，其中每个功能单元具有其自己的指令获取和解码块 ，并且每个功能单元具有其自己的用于程序存储的本地存储器; 并且其中响应于建立硬件单元的不同配置和切换互连的变化的应用指令序列，计算硬件执行单元和存储器单元被灵活地流水线化为具有不同顺序的可重新配置流水线级的可编程嵌入式处理器。

公开(公告)号：US20090300337A1

公开(公告)日：2009-12-03

申请号：US12156007

申请日：2008-05-29

申请人： Xiaolin Wang ,  Qian Wu ,  Benjamin Marshall ,  Fugui Wang ,  Gregory Pitarys ,  Ke Ning

发明人： Xiaolin Wang ,  Qian Wu ,  Benjamin Marshall ,  Fugui Wang ,  Gregory Pitarys ,  Ke Ning

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/30181 ,  G06F9/3867 ,  G06F9/3885 ,  G06F9/3897

摘要： Improved instruction set and core design, control and communication for programmable microprocessors is disclosed, involving the strategy for replacing centralized program sequencing in present-day and prior art processors with a novel distributed program sequencing wherein each functional unit has its own instruction fetch and decode block, and each functional unit has its own local memory for program storage; and wherein computational hardware execution units and memory units are flexibly pipelined as programmable embedded processors with reconfigurable pipeline stages of different order in response to varying application instruction sequences that establish different configurations and switching interconnections of the hardware units.

摘要翻译： 公开了针对可编程微处理器的改进的指令集和核心设计，控制和通信，其涉及用新的分布式程序排序代替当前和现有技术处理器中的集中程序排序的策略，其中每个功能单元具有其自己的指令获取和解码块 ，并且每个功能单元具有其自己的用于程序存储的本地存储器; 并且其中响应于建立硬件单元的不同配置和切换互连的变化的应用指令序列，计算硬件执行单元和存储器单元被灵活地流水线化为具有不同顺序的可重新配置流水线级的可编程嵌入式处理器。

公开(公告)号：US08078833B2

公开(公告)日：2011-12-13

申请号：US12156006

申请日：2008-05-29

申请人： Xiaolin Wang ,  Qian Wu ,  Benjamin Marshall ,  Fugui Wang ,  Ke Ning ,  Gregory Pitarys

发明人： Xiaolin Wang ,  Qian Wu ,  Benjamin Marshall ,  Fugui Wang ,  Ke Ning ,  Gregory Pitarys

IPC分类号： G06F15/00 ,  G06F15/76

CPC分类号： G06F5/015 ,  G06F9/30014 ,  G06F9/30181 ,  G06F9/3873 ,  G06F9/3875 ,  G06F9/3897

摘要： The invention resides in a flexible data pipeline structure for accommodating software computational instructions for varying application programs and having a programmable embedded processor with internal pipeline stages the order and length of which varies as fast as every clock cycle based on the instruction sequence in an application program preloaded into the processor, and wherein the processor includes a data switch matrix selectively and flexibly interconnecting pluralities of mathematical execution units and memory units in response to said instructions, and wherein the execution units are configurable to perform operations at different precisions of multi-bit arithmetic and logic operations and in a multi-level hierarchical architecture structure.

摘要翻译： 本发明涉及一种灵活的数据流水线结构，用于容纳用于变化的应用程序的软件计算指令，并且具有可编程嵌入式处理器，其具有内部流水线阶段，其顺序和长度基于应用程序中的指令序列而变化为每个时钟周期快 并且其中所述处理器包括数据交换矩阵，所述数据交换矩阵响应于所述指令选择性地和灵活地互连多个数学执行单元和存储器单元，并且其中所述执行单元可配置为以不同精度执行多位运算 逻辑运算和多级分层结构。

公开(公告)号：US20090300336A1

公开(公告)日：2009-12-03

申请号：US12156006

申请日：2008-05-29

申请人： Xiaolin Wang ,  Qian Wu ,  Benjamin Marshall ,  Fugui Wang ,  Ke Ning ,  Gregory Pitarys

发明人： Xiaolin Wang ,  Qian Wu ,  Benjamin Marshall ,  Fugui Wang ,  Ke Ning ,  Gregory Pitarys

IPC分类号： G06F9/302

CPC分类号： G06F5/015 ,  G06F9/30014 ,  G06F9/30181 ,  G06F9/3873 ,  G06F9/3875 ,  G06F9/3897

摘要： The invention resides in a flexible data pipeline structure for accommodating software computational instructions for varying application programs and having a programmable embedded processor with internal pipeline stages the order and length of which varies as fast as every clock cycle based on the instruction sequence in an application program preloaded into the processor, and wherein the processor includes a data switch matrix selectively and flexibly interconnecting pluralities of mathematical execution units and memory units in response to said instructions, and wherein the execution units are configurable to perform operations at different precisions of multi-bit arithmetic and logic operations and in a multi-level hierarchical architecture structure.

摘要翻译： 本发明涉及一种灵活的数据流水线结构，用于容纳用于变化的应用程序的软件计算指令，并且具有可编程嵌入式处理器，其具有内部流水线阶段，其顺序和长度基于应用程序中的指令序列而变化为每个时钟周期快 并且其中所述处理器包括数据交换矩阵，所述数据交换矩阵响应于所述指令选择性地和灵活地互连多个数学执行单元和存储器单元，并且其中所述执行单元可配置为以不同精度执行多位运算 逻辑运算和多级分层结构。

公开(公告)号：US06748435B1

公开(公告)日：2004-06-08

申请号：US09560323

申请日：2000-04-28

申请人： Fugui Wang ,  Sarit Mukherjee ,  Dennis Bushmitch

发明人： Fugui Wang ,  Sarit Mukherjee ,  Dennis Bushmitch

IPC分类号： G06F15173

CPC分类号： H04L47/29 ,  H04L43/00 ,  H04L43/0864 ,  H04L43/16 ,  H04L47/10 ,  H04L47/20 ,  H04L47/215 ,  H04L47/2458 ,  H04L47/31 ,  H04L47/326

摘要： Data packets are received by the REDP traffic conditioning marker from the upstream domain and each have a red, yellow, or green priority level. The traffic conditioning marker monitors the rate of green data packets flowing through the A random early demotion and promotion (REDP) traffic conditioning marker is located between an upstream domain and a downstream domain. If the rate exceeds a negotiated rate, the traffic conditioner randomly and fairly demotes green packets to yellow. If the rate is less than the negotiated rate, the traffic conditioner randomly and fairly promotes yellow packets to green. The traffic conditioner removes the phase effects that occur in conventional markers.

摘要翻译： 数据分组由REDP流量调节标记从上游域接收，每个具有红色，黄色或绿色优先级。 流量调节标记监测流经A随机早降降序（REDP）的绿色数据包的速率位于上游域和下游域之间。 如果速率超过协商速率，则流量调节器会随机地将绿色数据包降级为黄色。 如果速率低于协商速率，则流量调节器随机地并且公平地促进黄色分组变为绿色。 交通调节器消除常规标记中发生的相位效应。

公开(公告)号：US08843638B2

公开(公告)日：2014-09-23

申请号：US11955644

申请日：2007-12-13

申请人： Deepak Garg ,  Gopal Harikumar ,  Fugui Wang

发明人： Deepak Garg ,  Gopal Harikumar ,  Fugui Wang

IPC分类号： G06F15/16 ,  H04W36/00 ,  H04W36/02

CPC分类号： H04W36/0083 ,  H04W36/0005 ,  H04W36/0016 ,  H04W36/0088 ,  H04W36/0094 ,  H04W36/02 ,  H04W36/10

摘要： A connection is established between an access terminal and a first radio network controller through a first radio node. The first radio node is controllable primarily by the first radio network controller. The connection is maintained with the first radio network controller as the access terminal moves from a coverage area of the first radio node toward a coverage area of a second radio node. The second radio node is controllable primarily by a second radio network controller and controllable subordinately by the first radio network controller. A connection is also established through the second radio node. Upon a fulfillment of a predetermined criterion, the connection is transferred from the first radio network controller to the second radio network controller.

摘要翻译： 通过第一无线电节点在接入终端和第一无线电网络控制器之间建立连接。 第一无线电节点主要由第一无线电网络控制器控制。 当接入终端从第一无线电节点的覆盖区域移动到第二无线电节点的覆盖区域时，与第一无线电网络控制器保持连接。 第二无线电节点主要由第二无线电网络控制器控制并且可由第一无线电网络控制器从属地控制。 还通过第二无线电节点建立连接。 在实现预定标准时，连接从第一无线电网络控制器传送到第二无线电网络控制器。