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    SOI LATERAL MOSFET DEVICES
    1.
    发明申请
    SOI LATERAL MOSFET DEVICES 有权
    SOI侧向MOSFET器件

    公开(公告)号：US20130193509A1

    公开(公告)日：2013-08-01

    申请号：US13131779

    申请日：2010-08-10

    申请人： Xiaorong Luo ,  Florin Udrea

    发明人： Xiaorong Luo ,  Florin Udrea

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7813 ,  H01L27/1203 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7809 ,  H01L29/7812

    摘要： The present invention relates to a semiconductor power device and power integrated circuits (ICs). The lateral SOI MOSFET in the present comprises a trench gate extended to the dielectric buried layer, one or multiple dielectric trenches in the drift region, and a buried gate in said dielectric trench. The permittivity of the dielectric in said dielectric trench is lower than that of said active layer. Firstly, said dielectric trench not only greatly improves breakdown voltage, but also reduces pitch size. Secondly, the trench gate widens the effective conductive region in the vertical direction. Thirdly, dual gates of said trench gate and buried gate increase channel and current densities. Thereby, specific on-resistance and the power loss are reduced. The device of the present invention has many advantages, such as high voltage, high speed, low power loss, low cost and ease of integration. The device in the present invention is particularly suitable for power integrated circuits and RF power integrated circuits.

    摘要翻译： 本发明涉及半导体功率器件和功率集成电路（IC）。 本发明的横向SOI MOSFET包括延伸到电介质掩埋层的沟槽栅极，漂移区域中的一个或多个电介质沟槽以及所述电介质沟槽中的掩埋栅极。 电介质在所述电介质沟槽中的介电常数低于所述有源层的介电常数。 首先，所述电介质沟槽不仅大大提高了击穿电压，还降低了间距尺寸。 其次，沟槽栅极使垂直方向上的有效导电区域变宽。 第三，所述沟槽栅极和掩埋栅极的双栅极增加了沟道和电流密度。 从而，降低了特定导通电阻和功率损耗。 本发明的器件具有高电压，高速，低功耗，低成本，易集成等诸多优点。 本发明的器件特别适用于功率集成电路和RF功率集成电路。

    SOI lateral MOSFET devices
    2.
    发明授权
    SOI lateral MOSFET devices 有权
    SOI横向MOSFET器件

    公开(公告)号：US08716794B2

    公开(公告)日：2014-05-06

    申请号：US13131779

    申请日：2010-08-10

    申请人： Xiaorong Luo ,  Florin Udrea

    发明人： Xiaorong Luo ,  Florin Udrea

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7813 ,  H01L27/1203 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7809 ,  H01L29/7812

    摘要： The present invention relates to a semiconductor power device and power integrated circuits (ICs). The lateral SOI MOSFET in the present comprises a trench gate extended to the dielectric buried layer, one or multiple dielectric trenches in the drift region, and a buried gate in said dielectric trench. The permittivity of the dielectric in said dielectric trench is lower than that of said active layer. Firstly, said dielectric trench not only greatly improves breakdown voltage, but also reduces pitch size. Secondly, the trench gate widens the effective conductive region in the vertical direction. Thirdly, dual gates of said trench gate and buried gate increase channel and current densities. Thereby, specific on-resistance and the power loss are reduced. The device of the present invention has many advantages, such as high voltage, high speed, low power loss, low cost and ease of integration. The device in the present invention is particularly suitable for power integrated circuits and RF power integrated circuits.

    摘要翻译： 本发明涉及半导体功率器件和功率集成电路（IC）。 本发明的横向SOI MOSFET包括延伸到电介质掩埋层的沟槽栅极，漂移区域中的一个或多个电介质沟槽以及所述电介质沟槽中的掩埋栅极。 电介质在所述电介质沟槽中的介电常数低于所述有源层的介电常数。 首先，所述电介质沟槽不仅大大提高了击穿电压，还降低了间距尺寸。 其次，沟槽栅极使垂直方向上的有效导电区域变宽。 第三，所述沟槽栅极和掩埋栅极的双栅极增加了沟道和电流密度。 从而，降低了特定导通电阻和功率损耗。 本发明的器件具有高电压，高速，低功耗，低成本，易集成等诸多优点。 本发明的器件特别适用于功率集成电路和RF功率集成电路。

    PRODUCT JOIN DYNAMIC PARTITION ELIMINATION FOR MULTILEVEL PARTITIONING
    4.
    发明申请
    PRODUCT JOIN DYNAMIC PARTITION ELIMINATION FOR MULTILEVEL PARTITIONING 有权
    产品加入动态分区消除多重分区

    公开(公告)号：US20090037365A1

    公开(公告)日：2009-02-05

    申请号：US11830000

    申请日：2007-07-30

    申请人： Paul Sinclair ,  Xiaorong Luo ,  Mark Sirek

    发明人： Paul Sinclair ,  Xiaorong Luo ,  Mark Sirek

    IPC分类号： G06F17/30

    CPC分类号： G06F17/30474 ,  G06F17/30463

    摘要： A method of searching a multilevel partitioned database includes receiving a query data from the multilevel partitioned database. At least for one level partitions are dynamically included. For some levels, partitions may also be statically included for execution of the query. The query is the executed over the partitions that are both dynamically and statically included. In one example, the cost of joining two tables in a multilevel partitioned database includes determining level partitions that can be statically included, estimating level partitions that will be dynamically considered for the join, and determining a cost as a function of the estimated statically included level partitions and estimated dynamically included level partitions.

    摘要翻译： 搜索多级分区数据库的方法包括从多级分区数据库接收查询数据。 至少对于一个级别的动态包含分区。 对于某些级别，还可以静态地包含分区以执行查询。 该查询是在动态和静态包含的分区上执行的。 在一个示例中，在多级分区数据库中加入两个表的成本包括确定可静态包括的级别分区，估计将被连接进行动态考虑的级别分区，以及根据所估计的静态包含的级别来确定成本 分区和估计动态包含的级别分区。

    Product join dynamic partition elimination for multilevel partitioning
    7.
    发明授权
    Product join dynamic partition elimination for multilevel partitioning 有权
    产品加入动态分区消除多级分区

    公开(公告)号：US08396862B2

    公开(公告)日：2013-03-12

    申请号：US11830000

    申请日：2007-07-30

    申请人： Paul Sinclair ,  Xiaorong Luo ,  Mark Sirek

    发明人： Paul Sinclair ,  Xiaorong Luo ,  Mark Sirek

    IPC分类号： G06F7/00 ,  G06F17/30

    CPC分类号： G06F17/30474 ,  G06F17/30463

    摘要： A method of searching a multilevel partitioned database includes receiving a query data from the multilevel partitioned database. At least for one level partitions are dynamically included. For some levels, partitions may also be statically included for execution of the query. The query is the executed over the partitions that are both dynamically and statically included. In one example, the cost of joining two tables in a multilevel partitioned database includes determining level partitions that can be statically included, estimating level partitions that will be dynamically considered for the join, and determining a cost as a function of the estimated statically included level partitions and estimated dynamically included level partitions.

    摘要翻译： 搜索多级分区数据库的方法包括从多级分区数据库接收查询数据。 至少对于一个级别的动态包含分区。 对于某些级别，还可以静态地包含分区以执行查询。 该查询是在动态和静态包含的分区上执行的。 在一个示例中，在多级分区数据库中加入两个表的成本包括确定可静态包括的级别分区，估计将被连接进行动态考虑的级别分区，以及根据所估计的静态包含的级别来确定成本 分区和估计动态包含的级别分区。

    Trench-type semiconductor power devices
    9.
    发明授权
    Trench-type semiconductor power devices 有权
    沟槽型半导体功率器件

    公开(公告)号：US08890280B2

    公开(公告)日：2014-11-18

    申请号：US13033701

    申请日：2011-02-24

    申请人： Xiaorong Luo ,  Guoliang Yao ,  Tianfei Lei ,  Yuangang Wang ,  Bo Zhang

    发明人： Xiaorong Luo ,  Guoliang Yao ,  Tianfei Lei ,  Yuangang Wang ,  Bo Zhang

    IPC分类号： H01L23/58 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/739 ,  H01L21/265 ,  H01L29/08

    CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/66734 ,  H01L29/7397

    摘要： The present invention relates to a semiconductor device. The device comprises a semiconductor substrate. A semiconductor drift region is on the semiconductor substrate. The semiconductor drift region comprises a semiconductor region of a first conduction type and a semiconductor region of a second conduction type. The semiconductor region of the first conduction type and the semiconductor region of the second conduction type form a superjunction structure. A high-K dielectric is on the semiconductor substrate. The high-K dielectric is adjacent to the semiconductor region of the second conduction type. An active region is on the semiconductor drift region. A trench gate structure is on the high-K dielectric, the trench gate structure being adjacent to the active region. The semiconductor region of the second conduction type is formed by shallow angle ion implantation, thus its width is narrow and its concentration is high.

    摘要翻译： 本发明涉及一种半导体器件。 该器件包括半导体衬底。 半导体漂移区位于半导体衬底上。 半导体漂移区域包括第一导电类型的半导体区域和第二导电类型的半导体区域。 第一导电类型的半导体区域和第二导电类型的半导体区域形成超结构结构。 高K电介质在半导体衬底上。 高K电介质与第二导电类型的半导体区域相邻。 有源区位于半导体漂移区上。 沟槽栅极结构位于高K电介质上，沟槽栅极结构邻近有源区。 第二导电类型的半导体区域通过浅角离子注入形成，其宽度窄并且其浓度高。

    TRENCH-TYPE SEMICONDUCTOR POWER DEVICES
    10.
    发明申请
    TRENCH-TYPE SEMICONDUCTOR POWER DEVICES 有权
    TRENCH型半导体电源设备

    公开(公告)号：US20120168856A1

    公开(公告)日：2012-07-05

    申请号：US13033701

    申请日：2011-02-24

    申请人： Xiaorong Luo ,  Guoliang Yao ,  Tianfei Lei ,  Yuangang Wang ,  Bo Zhang

    发明人： Xiaorong Luo ,  Guoliang Yao ,  Tianfei Lei ,  Yuangang Wang ,  Bo Zhang

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/66734 ,  H01L29/7397

    摘要： The present invention relates to a semiconductor device. The device comprises a semiconductor substrate. A semiconductor drift region is on the semiconductor substrate. The semiconductor drift region comprises a semiconductor region of a first conduction type and a semiconductor region of a second conduction type. The semiconductor region of the first conduction type and the semiconductor region of the second conduction type form a superjunction structure. A high-K dielectric is on the semiconductor substrate. The high-K dielectric is adjacent to the semiconductor region of the second conduction type. An active region is on the semiconductor drift region. A trench gate structure is on the high-K dielectric, the trench gate structure being adjacent to the active region. The semiconductor region of the second conduction type is formed by shallow angle ion implantation, thus its width is narrow and its concentration is high.

    摘要翻译： 本发明涉及一种半导体器件。 该器件包括半导体衬底。 半导体漂移区位于半导体衬底上。 半导体漂移区域包括第一导电类型的半导体区域和第二导电类型的半导体区域。 第一导电类型的半导体区域和第二导电类型的半导体区域形成超结构结构。 高K电介质在半导体衬底上。 高K电介质与第二导电类型的半导体区域相邻。 有源区位于半导体漂移区上。 沟槽栅极结构位于高K电介质上，沟槽栅极结构邻近有源区。 第二导电类型的半导体区域通过浅角离子注入形成，其宽度窄并且其浓度高。