公开(公告)号：US10366001B1

公开(公告)日：2019-07-30

申请号：US15706255

申请日：2017-09-15

Applicant: Xilinx, Inc.

Inventor： Nithin Kumar Guggilla ,  Chaithanya Dudha ,  Krishna Garlapati ,  Chun Zhang ,  Fan Zhang ,  Anup Kumar Sultania

IPC: G06F12/00 ,  G06F12/02 ,  G06F1/3287 ,  G06F13/00 ,  G06F13/28

Abstract: Disclosed approaches of processing a circuit design include determining a subset of addresses of a first RAM of the circuit design that are accessed more often than a frequency threshold. A specification of a second RAM is created for the subset of addresses. A decoder circuit is added to the circuit design. The decoder circuit is configured to enable the second RAM and disable the first RAM in response to an input address in the subset of addresses, and to enable the first RAM and disable the second RAM in response to an input address other than addresses in the subset of addresses.