公开(公告)号：US08769448B1

公开(公告)日：2014-07-01

申请号：US13747940

申请日：2013-01-23

Applicant: Xilinx, Inc.

Inventor： Arvind Sundararajan ,  Nabeel Shirazi ,  Sean P. Caffee

IPC: G06F17/50

CPC classification number: G06F17/5022

Abstract: In one embodiment, a method is provided for processing a circuit design having first and second sets of ports configured to couple to respective first and second sets of ports of a device on a hardware platform. In a data-acquisition mode, the circuit design is simulated using a user-selectable plug-in that couples the ports of the circuit design to an interface circuit. During the simulation, the interface circuit communicates data between respective ports of the circuit design and ports of the device. In a deployment mode, the circuit design is implemented in the hardware platform, in which the first and second sets of ports of the circuit design are respectively coupled to the first and second sets of ports of the device.

Abstract translation: 在一个实施例中，提供了一种用于处理电路设计的方法，该电路设计具有配置成耦合到硬件平台上的设备的相应第一和第二组端口的第一和第二组端口。 在数据采集模式下，使用用户可选择的插件来模拟电路设计，该插件将电路设计的端口耦合到接口电路。 在仿真期间，接口电路在电路设计的各个端口和设备的端口之间传送数据。 在部署模式中，电路设计在硬件平台中实现，其中电路设计的第一和第二组端口分别耦合到设备的第一和第二组端口。

公开(公告)号：US09811618B1

公开(公告)日：2017-11-07

申请号：US13788189

申请日：2013-03-07

Applicant: Xilinx, Inc.

Inventor： Umang Parekh ,  Arvind Sundararajan ,  Sandeep Dutta

IPC: G06F17/50 ,  G06F15/78

CPC classification number: G06F17/5036 ,  G06F15/7867 ,  G06F17/5054

Abstract: A method is provided for simulating a program executable by a processor and a circuit design configured to communicate with the processor. A processor on a programmable IC is configured to execute the program. Programmable resources on the programmable IC are configured to implement a plurality of interface circuits. Each of the interface circuits is configured to communicate data between the processor and a simulation environment using a respective communication protocol. The interface circuits that uses a communication protocol used by the circuit design is enabled and other ones of the interface circuits are disabled. The circuit design is simulated in a simulation environment coupled to the programmable IC. During the simulating, the program is executed on the processor and data is communicated between the processor and the computing platform using the determined one of the plurality of interface circuits.

公开(公告)号：US08875073B1

公开(公告)日：2014-10-28

申请号：US14185832

申请日：2014-02-20

Applicant: Xilinx, Inc.

Inventor： Arvind Sundararajan ,  Jinsong Du

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/505

Abstract: A method relating generally to computer aided design is disclosed. In such method, a block-based model of a hardware realizable system is obtained. An internal gateway-in and an internal gateway-out of a module of the block-based model are identified. An interface protocol is assigned for the internal gateway-in and the internal gateway-out. Data type and data propagation for the module at the internal gateway-in and the internal gateway-out are analyzed. The internal gateway-in and the gateway-out are transformed into an input/output interface. Integrated code is generated for subsequent realization of the input/output interface in hardware.

Abstract translation: 公开了一般涉及计算机辅助设计的方法。 在这种方法中，获得了硬件可实现系统的基于块的模型。 识别基于块的模型的内部网关和模块的内部网关。 为内部网关和内部网关输出分配一个接口协议。 分析内部网关和内部网关的模块的数据类型和数据传播。 内部网关和网关出口被转换为输入/输出接口。 生成集成代码，用于随后在硬件中实现输入/输出接口。

公开(公告)号：US09183339B1

公开(公告)日：2015-11-10

申请号：US14538595

申请日：2014-11-11

Applicant: Xilinx, Inc.

Inventor： Nabeel Shirazi ,  David Robinson ,  Amit Kasat ,  Arvind Sundararajan

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/505

Abstract: A circuit design is created in a computer memory in response to user input to a computer processor. The circuit design has a static portion. A virtual socket is instantiated in the circuit design in response to user input, and one or more reconfigurable modules are instantiated in the virtual socket in response to user input. The static portion of the circuit design is coupled to the one or more reconfigurable modules, and configuration data are generated from the circuit design. The configuration data include a configuration bitstream corresponding to the static portion of the circuit design and one or more partial configuration bitstreams corresponding to the one or more reconfigurable modules.

Abstract translation: 响应于用户对计算机处理器的输入，在计算机存储器中创建电路设计。 电路设计有静态部分。 响应于用户输入，在电路设计中实例化虚拟插座，并且响应于用户输入在虚拟插座中实例化一个或多个可重新配置的模块。 电路设计的静态部分耦合到一个或多个可重新配置的模块，并且从电路设计产生配置数据。 配置数据包括对应于电路设计的静态部分的配置比特流和对应于一个或多个可重新配置模块的一个或多个部分配置比特流。