公开(公告)号：US11520717B1

公开(公告)日：2022-12-06

申请号：US17196669

申请日：2021-03-09

申请人： Xilinx, Inc.

发明人： David Clarke ,  Peter McColgan ,  Zachary Dickman ,  Jose Marques ,  Juan J. Noguera Serra ,  Tim Tuan ,  Baris Ozgul ,  Jan Langer

IPC分类号： G06F13/28 ,  G06F13/16

摘要： An integrated circuit having a data processing engine (DPE) array can include a plurality of memory tiles. A first memory tile can include a first direct memory access (DMA) engine, a first random-access memory (RAM) connected to the first DMA engine, and a first stream switch coupled to the first DMA engine. The first DMA engine may be coupled to a second RAM disposed in a second memory tile. The first stream switch may be coupled to a second stream switch disposed in the second memory tile.

公开(公告)号：US11443091B1

公开(公告)日：2022-09-13

申请号：US16945006

申请日：2020-07-31

申请人： Xilinx, Inc.

发明人： Peter McColgan ,  Baris Ozgul ,  David Clarke ,  Tim Tuan ,  Juan J. Noguera Serra ,  Goran H. K. Bilski ,  Jan Langer ,  Sneha Bhalchandra Date ,  Stephan Munz ,  Jose Marques

IPC分类号： G06F30/343 ,  G06F9/30 ,  G06F30/398 ,  G06F30/33

摘要： An integrated circuit includes a plurality of data processing engines (DPEs) DPEs. Each DPE may include a core configured to perform computations. A first DPE of the plurality of DPEs includes a first core coupled to an input cascade connection of the first core. The input cascade connection is directly coupled to a plurality of source cores of the plurality of DPEs. The input cascade connection includes a plurality of inputs, wherein each of the plurality of inputs is connected to a cascade output of a different one of the plurality of source cores. The input cascade connection is programmable to enable a selected one of the plurality of inputs.

公开(公告)号：US20230057903A1

公开(公告)日：2023-02-23

申请号：US17819872

申请日：2022-08-15

申请人： Xilinx, Inc.

发明人： David Clarke ,  Juan J. Noguera Serra ,  Javier Cabezas Rodriguez ,  Zachary Blaise Dickman ,  Pedro Miguel Parola Duarte ,  Jose Marques

IPC分类号： G06F9/445 ,  G06F9/50

摘要： An integrated circuit includes a data processing array. The data processing array includes a plurality of compute tiles each having a processor. The integrated circuit includes an array controller coupled to the data processing array. The array controller is adapted to configure the plurality of compute tiles of the data processing array to implement an application. The application specifies kernels executable by the processors and stream channels that convey data to the plurality of compute tiles. The array controller is configured to initiate execution of workloads by the data processing array as configured with the application.