公开(公告)号：US11520717B1

公开(公告)日：2022-12-06

申请号：US17196669

申请日：2021-03-09

Applicant: Xilinx, Inc.

Inventor： David Clarke ,  Peter McColgan ,  Zachary Dickman ,  Jose Marques ,  Juan J. Noguera Serra ,  Tim Tuan ,  Baris Ozgul ,  Jan Langer

IPC: G06F13/28 ,  G06F13/16

Abstract: An integrated circuit having a data processing engine (DPE) array can include a plurality of memory tiles. A first memory tile can include a first direct memory access (DMA) engine, a first random-access memory (RAM) connected to the first DMA engine, and a first stream switch coupled to the first DMA engine. The first DMA engine may be coupled to a second RAM disposed in a second memory tile. The first stream switch may be coupled to a second stream switch disposed in the second memory tile.

公开(公告)号：US11669464B1

公开(公告)日：2023-06-06

申请号：US16858417

申请日：2020-04-24

Applicant: XILINX, INC.

Inventor： Goran Hk Bilski ,  Baris Ozgul ,  David Clarke ,  Juan J. Noguera Serra ,  Jan Langer ,  Zachary Dickman ,  Sneha Bhalchandra Date ,  Tim Tuan

IPC: G06F12/1081 ,  G06F12/06 ,  G06F9/52 ,  G06F15/78 ,  G06F12/02

CPC classification number: G06F12/1081 ,  G06F9/524 ,  G06F12/0246 ,  G06F12/0607 ,  G06F15/7807

Abstract: Examples herein describe performing non-sequential DMA read and writes. Rather than storing data sequentially, a DMA engine can write data into memory using non-sequential memory addresses. A data processing engine (DPE) controller can submit a first job using first parameters that instruct the DMA engine to store data using a first non-sequential write pattern. The DPE controller can also submit a second job using second parameters that instruct the DMA engine to store data using a second, different non-sequential write pattern. In this manner, the DMA engine can switch to performing DMA writes using different non-sequential patterns. Similarly, the DMA engine can use non-sequential reads to retrieve data from memory. When performing a first DMA read, the DMA engine can retrieve data from memory using a first sequential pattern and then perform a second DMA read where data is retrieved from memory using a second non-sequential read pattern.

公开(公告)号：US20190303328A1

公开(公告)日：2019-10-03

申请号：US15944617

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Goran H.K. Balski ,  Juan J. Noguera Serra ,  David Clarke ,  Tim Tuan ,  Peter McColgan ,  Zachary Dickman ,  Baris Ozgul ,  Jan Langer

IPC: G06F13/40 ,  G06F13/16

Abstract: A device may include a plurality of data processing engines, a subsystem, and an SoC interface block coupled to the plurality of data processing engines and the subsystem. The SoC interface block may be configured to exchange data between the subsystem and the plurality of data processing engines.