公开(公告)号：US10824584B1

公开(公告)日：2020-11-03

申请号：US15944295

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Sneha Bhalchandra Date ,  Jan Langer ,  Baris Ozgul ,  Goran H K Bilski

IPC: G06F9/24 ,  G06F15/177 ,  G06F15/173 ,  G06F15/80 ,  G06F9/4401

Abstract: A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying operation of a first kernel of a first subset of the DPEs of the array of DPEs, reconfiguration of a second subset of the DPEs of the array of DPEs.

公开(公告)号：US11599498B1

公开(公告)日：2023-03-07

申请号：US17068697

申请日：2020-10-12

Applicant: XILINX, INC.

Inventor： Juan J. Noguera Serra ,  Sneha Bhalchandra Date ,  Jan Langer ,  Baris Ozgul ,  Goran Hk Bilski

IPC: G06F9/00 ,  G06F15/177 ,  G06F15/80 ,  G06F15/173 ,  G06F9/4401

Abstract: A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying operation of a first kernel of a first subset of the DPEs of the array of DPEs, reconfiguration of a second subset of the DPEs of the array of DPEs.

公开(公告)号：US11443091B1

公开(公告)日：2022-09-13

申请号：US16945006

申请日：2020-07-31

Applicant: Xilinx, Inc.

Inventor： Peter McColgan ,  Baris Ozgul ,  David Clarke ,  Tim Tuan ,  Juan J. Noguera Serra ,  Goran H. K. Bilski ,  Jan Langer ,  Sneha Bhalchandra Date ,  Stephan Munz ,  Jose Marques

IPC: G06F30/343 ,  G06F9/30 ,  G06F30/398 ,  G06F30/33

Abstract: An integrated circuit includes a plurality of data processing engines (DPEs) DPEs. Each DPE may include a core configured to perform computations. A first DPE of the plurality of DPEs includes a first core coupled to an input cascade connection of the first core. The input cascade connection is directly coupled to a plurality of source cores of the plurality of DPEs. The input cascade connection includes a plurality of inputs, wherein each of the plurality of inputs is connected to a cascade output of a different one of the plurality of source cores. The input cascade connection is programmable to enable a selected one of the plurality of inputs.

公开(公告)号：US11372803B2

公开(公告)日：2022-06-28

申请号：US15944408

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Goran H. K. Bilski ,  Juan J. Noguera Serra ,  Baris Ozgul ,  Jan Langer ,  David Clarke ,  Sneha Bhalchandra Date

IPC: G06F15/80 ,  G06F13/40 ,  G06F15/173 ,  G06F13/16

Abstract: An example data processing engine (DPE) for a DPE array in an integrated circuit (IC) includes: a core; a memory including a data memory and a program memory, the program memory coupled to the core, the data memory coupled to the core and including at least one connection to a respective at least one additional core external to the DPE; support circuitry including hardware synchronization circuitry and direct memory access (DMA) circuitry each coupled to the data memory; streaming interconnect coupled to the DMA circuitry and the core; and memory-mapped interconnect coupled to the core, the memory, and the support circuitry.

公开(公告)号：US11669464B1

公开(公告)日：2023-06-06

申请号：US16858417

申请日：2020-04-24

Applicant: XILINX, INC.

Inventor： Goran Hk Bilski ,  Baris Ozgul ,  David Clarke ,  Juan J. Noguera Serra ,  Jan Langer ,  Zachary Dickman ,  Sneha Bhalchandra Date ,  Tim Tuan

IPC: G06F12/1081 ,  G06F12/06 ,  G06F9/52 ,  G06F15/78 ,  G06F12/02

CPC classification number: G06F12/1081 ,  G06F9/524 ,  G06F12/0246 ,  G06F12/0607 ,  G06F15/7807

Abstract: Examples herein describe performing non-sequential DMA read and writes. Rather than storing data sequentially, a DMA engine can write data into memory using non-sequential memory addresses. A data processing engine (DPE) controller can submit a first job using first parameters that instruct the DMA engine to store data using a first non-sequential write pattern. The DPE controller can also submit a second job using second parameters that instruct the DMA engine to store data using a second, different non-sequential write pattern. In this manner, the DMA engine can switch to performing DMA writes using different non-sequential patterns. Similarly, the DMA engine can use non-sequential reads to retrieve data from memory. When performing a first DMA read, the DMA engine can retrieve data from memory using a first sequential pattern and then perform a second DMA read where data is retrieved from memory using a second non-sequential read pattern.

公开(公告)号：US11336287B1

公开(公告)日：2022-05-17

申请号：US17196574

申请日：2021-03-09

Applicant: Xilinx, Inc.

Inventor： Javier Cabezas Rodriguez ,  Juan J. Noguera Serra ,  David Clarke ,  Sneha Bhalchandra Date ,  Tim Tuan ,  Peter McColgan ,  Jan Langer ,  Baris Ozgul

IPC: H03K19/1776 ,  H03K19/17704 ,  H03K19/17768 ,  H03K19/17758 ,  H03K19/17796

Abstract: An integrated circuit can include a data processing engine (DPE) array having a plurality of tiles. The plurality of tiles can include a plurality of DPE tiles, wherein each DPE tile includes a stream switch, a core configured to perform operations, and a memory module. The plurality of tiles can include a plurality of memory tiles, wherein each memory tile includes a stream switch, a direct memory access (DMA) engine, and a random-access memory. The DMA engine of each memory tile may be configured to access the random-access memory within the same memory tile and the random-access memory of at least one other memory tile. Selected ones of the plurality of DPE tiles may be configured to access selected ones of the plurality of memory tiles via the stream switches.

公开(公告)号：US20190303347A1

公开(公告)日：2019-10-03

申请号：US15944408

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Goran H.K. Bilski ,  Juan J. Noguera Serra ,  Baris Ozgul ,  Jan Langer ,  David Clarke ,  Sneha Bhalchandra Date

IPC: G06F15/80

Abstract: An example data processing engine (DPE) for a DPE array in an integrated circuit (IC) includes: a core; a memory including a data memory and a program memory, the program memory coupled to the core, the data memory coupled to the core and including at least one connection to a respective at least one additional core external to the DPE; support circuitry including hardware synchronization circuitry and direct memory access (DMA) circuitry each coupled to the data memory; streaming interconnect coupled to the DMA circuitry and the core; and memory-mapped interconnect coupled to the core, the memory, and the support circuitry.

公开(公告)号：US12105667B2

公开(公告)日：2024-10-01

申请号：US18114850

申请日：2023-02-27

Applicant: XILINX, INC.

Inventor： Juan J. Noguera Serra ,  Sneha Bhalchandra Date ,  Jan Langer ,  Baris Ozgul ,  Goran H. k. Bilski

IPC: G06F9/24 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F1/24 ,  G06F9/4401

CPC classification number: G06F15/177 ,  G06F15/17306 ,  G06F15/80 ,  G06F1/24 ,  G06F9/4401 ,  G06F9/4411

Abstract: A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying operation of a first kernel of a first subset of the DPEs of the array of DPEs, reconfiguration of a second subset of the DPEs of the array of DPEs.

公开(公告)号：US11296707B1

公开(公告)日：2022-04-05

申请号：US17196574

申请日：2021-03-09

Applicant: Xilinx, Inc.

Inventor： Javier Cabezas Rodriguez ,  Juan J. Noguera Serra ,  David Clarke ,  Sneha Bhalchandra Date ,  Tim Tuan ,  Peter McColgan ,  Jan Langer ,  Baris Ozgul

IPC: H03K19/1776 ,  H03K19/17704 ,  H03K19/17768 ,  H03K19/17758 ,  H03K19/17796

Abstract: An integrated circuit can include a data processing engine (DPE) array having a plurality of tiles. The plurality of tiles can include a plurality of DPE tiles, wherein each DPE tile includes a stream switch, a core configured to perform operations, and a memory module. The plurality of tiles can include a plurality of memory tiles, wherein each memory tile includes a stream switch, a direct memory access (DMA) engine, and a random-access memory. The DMA engine of each memory tile may be configured to access the random-access memory within the same memory tile and the random-access memory of at least one other memory tile. Selected ones of the plurality of DPE tiles may be configured to access selected ones of the plurality of memory tiles via the stream switches.

公开(公告)号：US20200076660A1

公开(公告)日：2020-03-05

申请号：US16117605

申请日：2018-08-30

Applicant: Xilinx, Inc.

Inventor： Kaushik Barman ,  Parag Dighe ,  Baris Ozgul ,  Sneha Bhalchandra Date

IPC: H04L27/26 ,  G01R19/04 ,  G01R19/25

Abstract: Techniques related to a data processing engine for an integrated circuit (IC) are described. In an example, a method is provided for vectorized peak detection. The method includes dividing a set of data samples of a data signal, corresponding to a peak detection window (PDW), into a plurality of subsets of data samples each comprising a number of data samples. The method includes performing vector operations on each of the plurality of subsets of data samples. The method includes determining a running index of a sample with a maximum amplitude over the PDW based on the vector operations.