公开(公告)号：US20230053537A1

公开(公告)日：2023-02-23

申请号：US17819879

申请日：2022-08-15

Applicant: Xilinx, Inc.

Inventor： Baris Ozgul ,  David Clarke ,  Peter McColgan ,  Stephan Munz ,  Dylan Stuart ,  Pedro Miguel Parola Duarte ,  Juan J. Noguera Serra

IPC: G06F13/16 ,  G06F13/28 ,  G06F17/16 ,  G06N3/063

Abstract: Using multiple overlays with a data processing array includes loading an application in a data processing array. The data processing array includes a plurality of compute tiles each having a processor. The application specifies kernels executable by the processors and implements stream channels that convey data to the plurality of compute tiles. During runtime of the application, a plurality of overlays are sequentially implemented in the data processing array. Each overlay implements a different mode of data movement in the data processing array via the stream channels. For each overlay implemented, a workload is performed by moving data to the plurality of compute tiles based on the respective mode of data movement.

公开(公告)号：US12067406B2

公开(公告)日：2024-08-20

申请号：US17819879

申请日：2022-08-15

Applicant: Xilinx, Inc.

Inventor： Baris Ozgul ,  David Clarke ,  Peter McColgan ,  Stephan Münz ,  Dylan Stuart ,  Pedro Miguel Parola Duarte ,  Juan J. Noguera Serra

IPC: G06F9/445 ,  G06F9/50 ,  G06F13/16 ,  G06F13/28 ,  G06F17/16 ,  G06N3/063

CPC classification number: G06F9/44505 ,  G06F9/5083 ,  G06F13/1673 ,  G06F13/28 ,  G06F17/16 ,  G06N3/063

Abstract: Using multiple overlays with a data processing array includes loading an application in a data processing array. The data processing array includes a plurality of compute tiles each having a processor. The application specifies kernels executable by the processors and implements stream channels that convey data to the plurality of compute tiles. During runtime of the application, a plurality of overlays are sequentially implemented in the data processing array. Each overlay implements a different mode of data movement in the data processing array via the stream channels. For each overlay implemented, a workload is performed by moving data to the plurality of compute tiles based on the respective mode of data movement.

公开(公告)号：US20230376437A1

公开(公告)日：2023-11-23

申请号：US17663824

申请日：2022-05-17

Applicant: Xilinx, Inc.

Inventor： David Patrick Clarke ,  Peter McColgan ,  Juan J. Noguera Serra ,  Tim Tuan ,  Saurabh Mathur ,  Amarnath Kasibhatla ,  Javier Cabezas Rodriguez ,  Pedro Miguel Parola Duarte ,  Zachary Blaise Dickman

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F2213/28

Abstract: An integrated circuit (IC) can include a data processing array including a plurality of compute tiles arranged in a grid. The IC can include an array interface coupled to the data processing array. The array interface includes a plurality of interface tiles. Each interface tile includes a plurality of direct memory access circuits. The IC can include a network-on-chip (NoC) coupled to the array interface. Each direct memory access circuit is communicatively linked to the NoC via an independent communication channel.

公开(公告)号：US12164451B2

公开(公告)日：2024-12-10

申请号：US17663824

申请日：2022-05-17

Applicant: Xilinx, Inc.

Inventor： David Patrick Clarke ,  Peter McColgan ,  Juan J. Noguera Serra ,  Tim Tuan ,  Saurabh Mathur ,  Amarnath Kasibhatla ,  Javier Cabezas Rodriguez ,  Pedro Miguel Parola Duarte ,  Zachary Blaise Dickman

IPC: G06F13/28 ,  G06F15/80

Abstract: An integrated circuit (IC) can include a data processing array including a plurality of compute tiles arranged in a grid. The IC can include an array interface coupled to the data processing array. The array interface includes a plurality of interface tiles. Each interface tile includes a plurality of direct memory access circuits. The IC can include a network-on-chip (NoC) coupled to the array interface. Each direct memory access circuit is communicatively linked to the NoC via an independent communication channel.

公开(公告)号：US20230057903A1

公开(公告)日：2023-02-23

申请号：US17819872

申请日：2022-08-15

Applicant: Xilinx, Inc.

Inventor： David Clarke ,  Juan J. Noguera Serra ,  Javier Cabezas Rodriguez ,  Zachary Blaise Dickman ,  Pedro Miguel Parola Duarte ,  Jose Marques

IPC: G06F9/445 ,  G06F9/50

Abstract: An integrated circuit includes a data processing array. The data processing array includes a plurality of compute tiles each having a processor. The integrated circuit includes an array controller coupled to the data processing array. The array controller is adapted to configure the plurality of compute tiles of the data processing array to implement an application. The application specifies kernels executable by the processors and stream channels that convey data to the plurality of compute tiles. The array controller is configured to initiate execution of workloads by the data processing array as configured with the application.