公开(公告)号：US09006030B1

公开(公告)日：2015-04-14

申请号：US14100678

申请日：2013-12-09

Applicant: Xilinx, Inc.

Inventor： Woon-Seong Kwon ,  Suresh Ramalingam ,  Paul Y. Wu ,  Manoj Nachnani

IPC: H01L23/492 ,  H01L21/58 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: An integrated circuit includes a stacked conductive layer interposer and a first die at least partially encapsulated in a mold material. The first die is mechanically and electrically attached to a top surface of the stacked conductive layer interposer using solder bumps. The integrated circuit further includes a first warpage correction layer.

Abstract translation: 集成电路包括层叠的导电层插入件和至少部分地封装在模具材料中的第一模具。 使用焊料凸块将第一裸片机械和电连接到堆叠的导电层插入件的顶表面。 集成电路还包括第一翘曲校正层。