公开(公告)号：US09083347B1

公开(公告)日：2015-07-14

申请号：US14280188

申请日：2014-05-16

Applicant: Xilinx, Inc.

Inventor： Riyas Noorudeen Remla ,  Rajesh Bansal

IPC: H03K21/38

CPC classification number: H03K21/38

Abstract: Circuits and methods for capturing internal signal values in a circuit before, during, and after a trigger event are disclosed. For example, a circuit can include a shift register configured to receive data values of an input data set over a plurality of cycles, and a counter unit configured to receive a trigger signal and to output the trigger signal after a number of cycles following the receiving of the trigger signal, where the trigger signal indicates a trigger event. The circuit can also include a switch configured to receive the trigger signal from the counter unit and to open a connection between an input interface and the shift register in response to receiving the trigger signal.

Abstract translation: 公开了在触发事件之前，期间和之后捕获电路中的内部信号值的电路和方法。 例如，电路可以包括被配置为在多个周期中接收输入数据集的数据值的移位寄存器，以及被配置为接收触发信号并且在接收之后的多个周期之后输出触发信号的计数器单元 触发信号，其中触发信号指示触发事件。 电路还可以包括被配置为从计数器单元接收触发信号并且响应于接收到触发信号而打开输入接口和移位寄存器之间的连接的开关。

公开(公告)号：US10161999B1

公开(公告)日：2018-12-25

申请号：US15091376

申请日：2016-04-05

Applicant: Xilinx, Inc.

Inventor： Heera Nand ,  Niloy Roy ,  Mahesh Sankroj ,  Siddharth Rele ,  Riyas Noorudeen Remla ,  Rajesh Bansal ,  Bradley K. Fross

IPC: G06F17/50 ,  G01R31/317 ,  G01R31/3177

Abstract: Approaches for capturing states of signals of a circuit-under-test are disclosed. A logic analyzer circuit is coupled to the circuit-under-test and is configured to receive a plurality of probe signals and a plurality of trigger signals from the circuit-under-test. The logic analyzer circuit inputs data identifying a subset of the probe signals and a subset of the trigger signals. The logic analyzer circuit selects the subset of trigger signals for input to trigger logic and selects the subset of probe signals in the logic analyzer circuit after the logic analyzer circuit and the circuit-under-test are active. The logic analyzer circuit samples states of the subset of probe signals in response to the trigger logic and stores the sampled states of the subset of probe signals in a memory.