公开(公告)号：US10481814B1

公开(公告)日：2019-11-19

申请号：US15635646

申请日：2017-06-28

Applicant: Xilinx, Inc.

Inventor： Heera Nand ,  Amit Kasat

IPC: G06F17/50 ,  G06F3/06

Abstract: Implementing a kernel as circuitry in an integrated circuit can include determining, using a processor, memory access operations and work operations from kernel program code and generating, using the processor, a circuit design from the kernel program code. The circuit design implements a circuit architecture having a memory access circuit configured to perform the memory access operations and an execution circuit configured to perform the work operations concurrently with the memory access operations.

公开(公告)号：US11539770B1

公开(公告)日：2022-12-27

申请号：US17201172

申请日：2021-03-15

Applicant: Xilinx, Inc.

Inventor： Heera Nand ,  Sahil Goyal

IPC: H04L65/61 ,  G06F30/392 ,  G06F111/02

Abstract: Providing host-to-kernel streaming support can include determining a platform circuitry for use with a streaming kernel of a circuit design. The streaming kernel is configured for implementation in a user circuitry region of an integrated circuit (IC) to perform tasks offloaded from a host computer. The platform circuitry is configured for implementation in a static circuitry region of the IC. The platform circuitry is configured to establish a communication link with the host computer. An adaptable streaming controller can be inserted within the circuit design. The adaptable streaming controller is configured for implementation in the user circuitry region and connects to the streaming kernel. The adaptable streaming controller further communicatively links the streaming kernel with the platform circuitry. The adaptable streaming controller can be parameterized for exchanging data between the platform circuitry and the streaming kernel based, at least in part, on a type of the platform circuitry.

公开(公告)号：US09864828B1

公开(公告)日：2018-01-09

申请号：US14857634

申请日：2015-09-17

Applicant: Xilinx, Inc.

Inventor： Susheel Kumar Puthana ,  Stephen P. Rozum ,  Sudipto Chakraborty ,  David A. Knol ,  Yong Li ,  Fernando J. Martinez Vallina ,  Sonal Santan ,  Nabeel Shirazi ,  Salil R. Raje ,  Ethan T. Parker ,  Suman Kumar Timmireddy ,  Heera Nand

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5072

Abstract: Implementing hardware accelerators using programmable integrated circuits may include performing, using a processor, a design flow on a static circuit design. The static circuit design may specify a region reserved for a hardware accelerator and a static region comprising interface circuitry configured to couple the hardware accelerator with an external node. The design flow may generate an implemented static circuit design. Metadata describing the interface circuitry may be generated using a processor. A device support archive including the implemented static circuit design and the metadata may be written, using the processor, to a computer readable storage medium.

公开(公告)号：US10161999B1

公开(公告)日：2018-12-25

申请号：US15091376

申请日：2016-04-05

Applicant: Xilinx, Inc.

Inventor： Heera Nand ,  Niloy Roy ,  Mahesh Sankroj ,  Siddharth Rele ,  Riyas Noorudeen Remla ,  Rajesh Bansal ,  Bradley K. Fross

IPC: G06F17/50 ,  G01R31/317 ,  G01R31/3177

Abstract: Approaches for capturing states of signals of a circuit-under-test are disclosed. A logic analyzer circuit is coupled to the circuit-under-test and is configured to receive a plurality of probe signals and a plurality of trigger signals from the circuit-under-test. The logic analyzer circuit inputs data identifying a subset of the probe signals and a subset of the trigger signals. The logic analyzer circuit selects the subset of trigger signals for input to trigger logic and selects the subset of probe signals in the logic analyzer circuit after the logic analyzer circuit and the circuit-under-test are active. The logic analyzer circuit samples states of the subset of probe signals in response to the trigger logic and stores the sampled states of the subset of probe signals in a memory.

公开(公告)号：US09465903B1

公开(公告)日：2016-10-11

申请号：US14546684

申请日：2014-11-18

Applicant: Xilinx, Inc.

Inventor： Suman Kumar Timmireddy ,  Heera Nand ,  Awdhesh Kumar Sahu ,  Brendan M. O'Higgins ,  David A. Knol ,  Siddharth Rele

IPC: G06F17/50 ,  G06F19/00 ,  H03K19/177 ,  G06F21/12 ,  G06F15/78

CPC classification number: G06F17/5054 ,  G06F15/7867 ,  G06F17/50 ,  G06F17/5022 ,  G06F21/125 ,  H03K19/17728 ,  H03K19/17748

Abstract: A method of implementing a circuit design in a circuit design tool for configuration in a programmable integrated circuit (IC) connected to components on a circuit board is described. The method includes processing a first file associated with the circuit board to obtain descriptions of circuit board interfaces of the components on the circuit board; displaying a graphic user interface (GUI) of the circuit design tool to connect a circuit board interface described in the first file with a circuit design interface in the circuit design; generating physical constraints on the circuit design interface with respect to input/outputs of the programmable IC described as being connected to the selected circuit board interface; and generating a bitstream to configure the programmable IC. The bitstream includes a physical implementation of the circuit design satisfying the physical constraints.

Abstract translation: 描述了在用于配置在与电路板上的部件连接的可编程集成电路（IC）中的电路设计工具中实现电路设计的方法。 该方法包括处理与电路板相关联的第一文件以获得电路板上组件的电路板接口的描述; 显示所述电路设计工具的图形用户界面（GUI），以将所述第一文件中描述的电路板接口与所述电路设计中的电路设计接口连接; 相对于被描述为连接到所选择的电路板接口的可编程IC的输入/输出，在电路设计接口上产生物理约束; 以及生成比特流以配置可编程IC。 比特流包括满足物理约束的电路设计的物理实现。