公开(公告)号：US09054684B1

公开(公告)日：2015-06-09

申请号：US13848689

申请日：2013-03-21

Applicant: Xilinx, Inc.

Inventor： Santosh Kumar Sood ,  Praful Jain ,  Ramakrishna K. Tanikella

IPC: H03K5/125 ,  G01R31/3181

CPC classification number: H03K5/125 ,  G01R31/31816 ,  G01R31/318519

Abstract: A circuit block within an integrated circuit includes a multiplexor (225, 625) configured to pass either a first signal or a second signal, wherein the first signal is independent of the second signal. The circuit block further includes a first flip-flop (210, 610) configured to receive an output of the multiplexor and a second flip-flop (215, 615) configured to receive the second signal. In a first mode of operation, the multiplexor passes the first signal to the first flip-flop. Further, the first flip flop and the second flip-flop operate independently of one another. In a second mode of operation, the multiplexor passes the second signal to the first flip-flop. Further, the first flip-flop and the second flip-flop both receive the second signal.

Abstract translation: 集成电路内的电路块包括经配置以通过第一信号或第二信号的多路复用器（225,625），其中第一信号独立于第二信号。 电路块还包括被配置为接收多路复用器的输出的第一触发器（210,610）和被配置为接收第二信号的第二触发器（215,615）。 在第一操作模式中，多路复用器将第一信号传递到第一触发器。 此外，第一触发器和第二触发器彼此独立地操作。 在第二操作模式中，多路复用器将第二信号传递到第一触发器。 此外，第一触发器和第二触发器都接收第二信号。

公开(公告)号：US10804255B1

公开(公告)日：2020-10-13

申请号：US16409175

申请日：2019-05-10

Applicant: Xilinx, Inc.

Inventor： Sundeep Ram Gopal Agarwal ,  Ramakrishna K. Tanikella

IPC: H01L25/18 ,  H03K3/037

Abstract: A circuit for transmitting signals in an integrated circuit device is described. The circuit comprises a first die; a second die stacked on the first die; and a buffer transmitting data between the first die and the second die; wherein a first inverter of the buffer is on the first die, and a second inverter of the buffer is on the second die. A method of transmitting signals in an integrated circuit device is also described.

公开(公告)号：US09000529B1

公开(公告)日：2015-04-07

申请号：US13666159

申请日：2012-11-01

Applicant: Xilinx, Inc.

Inventor： Praful Jain ,  James Karp ,  Michael J. Hart ,  Ramakrishna K. Tanikella

IPC: H01L21/70 ,  H01L29/06

CPC classification number: H01L29/0646 ,  H01L27/0207 ,  H03K19/0033

Abstract: A circuit includes a complimentary metal-oxide semiconductor (CMOS) storage element implemented within a p-type substrate and an n-well implemented within the p-type substrate that is independent of the storage element. The n-well and the storage element are separated by a minimum distance in which the p-type substrate includes no n-well.

Abstract translation: 电路包括实现在p型衬底内的互补金属氧化物半导体（CMOS）存储元件和在p型衬底内实现的与存储元件无关的n阱。 n阱和存储元件分开最小距离，其中p型衬底不包括n阱。