公开(公告)号：US09496871B1

公开(公告)日：2016-11-15

申请号：US14462370

申请日：2014-08-18

Applicant: Xilinx, Inc.

Inventor： Benjamin S. Devlin ,  Brian C. Gaide ,  Santosh Kumar Sood

IPC: G11C5/14 ,  H03K19/00 ,  H03K19/177

CPC classification number: H03K19/0016 ,  G11C5/063 ,  G11C5/147 ,  H03K19/17748

Abstract: An integrated circuit includes: a voltage rail; voltage control circuitry coupled to the voltage rail; and a circuit block coupled to the voltage control circuitry; wherein the voltage control circuitry is selectively configurable to operate the circuit block in at least a first mode of operation and a second mode of operation; wherein in the first mode of operation, the circuit block receives a voltage that is substantially the same as a voltage of the voltage rail; and wherein in the second mode of operation, the circuit block receives a voltage that is less than the voltage of the voltage rail by a threshold voltage.

Abstract translation: 集成电路包括：电压轨; 耦合到电压轨的电压控制电路; 以及耦合到所述电压控制电路的电路块; 其中所述电压控制电路被选择性地配置为在至少第一操作模式和第二操作模式中操作所述电路块; 其中在所述第一操作模式中，所述电路块接收与所述电压轨的电压基本相同的电压; 并且其中在所述第二操作模式中，所述电路块接收的电压小于所述电压轨的电压阈值电压。

公开(公告)号：US09665671B1

公开(公告)日：2017-05-30

申请号：US14995678

申请日：2016-01-14

Applicant: Xilinx, Inc.

Inventor： Santosh Kumar Sood

IPC: G06F17/50 ,  H03K19/177 ,  G06F1/32

CPC classification number: G06F17/5027 ,  G06F1/3287 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5081 ,  H03K19/17744 ,  H03K19/1776 ,  H03K19/17772

Abstract: Emulating power gating includes identifying an isolation circuit having a first input coupled to an output of a first power domain, a second input coupled to an isolation signal, and an output coupled to an input of a second power domain; removing a power gate circuit configured to selectively decouple the first power domain from a power supply responsive to a power gate signal; and decoupling the first input of the isolation circuit from the output of the first power domain. A power gate emulation circuit is inserted using a processor. The power gate emulation circuit is coupled to the isolation signal, the power gate signal, and the output of the first power domain.

公开(公告)号：US09438244B2

公开(公告)日：2016-09-06

申请号：US14526192

申请日：2014-10-28

Applicant: Xilinx, Inc.

Inventor： Santosh Kumar Sood ,  Brian C. Gaide ,  Steven P. Young

IPC: G05F1/10 ,  H03K19/177 ,  H03K19/00

CPC classification number: H03K19/17784 ,  H03K19/0008 ,  H03K19/0016

Abstract: A circuit for controlling power within an integrated circuit comprises a plurality of circuit blocks; a global control signal routed within the integrated circuit; and a plurality of power control blocks. Each power control block is coupled to a corresponding circuit block of the plurality of circuit bocks and has a first input coupled to receive a reference voltage and a second input coupled to receive the global control signal. The global control signal enables, for each circuit block, the coupling of the reference voltage to the corresponding circuit block. A method of controlling power within an integrated circuit is also disclosed.

Abstract translation: 用于控制集成电路内的电力的电路包括多个电路块; 在集成电路内布线的全局控制信号; 和多个功率控制块。 每个功率控制块耦合到多个电路块的相应电路块，并且具有耦合以接收参考电压的第一输入和耦合以接收全局控制信号的第二输入。 对于每个电路块，全局控制信号使得参考电压与对应的电路块的耦合。 还公开了一种控制集成电路内的功率的方法。

公开(公告)号：US20160098059A1

公开(公告)日：2016-04-07

申请号：US14503845

申请日：2014-10-01

Applicant: Xilinx, Inc.

Inventor： Santosh Kumar Sood

IPC: G06F1/08

CPC classification number: G06F1/08 ,  G06F1/12

Abstract: A circuit for processing data in an integrated circuit device comprises a selection circuit; a first register coupled to a first output of the selection circuit; a second register implemented as a latch and coupled to a second output of the selection circuit; and a signal line coupled between the output of the first register and an input of the selection circuit. The selection circuit enables the coupling of an output signal of the first register to an input of the second register. A method of processing data in an integrated circuit device is also disclosed.

Abstract translation: 一种用于在集成电路装置中处理数据的电路包括选择电路; 耦合到所述选择电路的第一输出的第一寄存器; 第二寄存器，被实现为锁存器并耦合到所述选择电路的第二输出; 以及耦合在第一寄存器的输出和选择电路的输入之间的信号线。 选择电路使得能够将第一寄存器的输出信号耦合到第二寄存器的输入端。 还公开了一种在集成电路器件中处理数据的方法。

公开(公告)号：US20160118988A1

公开(公告)日：2016-04-28

申请号：US14526192

申请日：2014-10-28

Applicant: Xilinx, Inc.

Inventor： Santosh Kumar Sood ,  Brian C. Gaide ,  Steven P. Young

IPC: H03K19/177 ,  H03K19/00

CPC classification number: H03K19/17784 ,  H03K19/0008 ,  H03K19/0016

Abstract: A circuit for controlling power within an integrated circuit comprises a plurality of circuit blocks; a global control signal routed within the integrated circuit; and a plurality of power control blocks. Each power control block is coupled to a corresponding circuit block of the plurality of circuit bocks and has a first input coupled to receive a reference voltage and a second input coupled to receive the global control signal. The global control signal enables, for each circuit block, the coupling of the reference voltage to the corresponding circuit block. A method of controlling power within an integrated circuit is also disclosed.

Abstract translation: 用于控制集成电路内的电力的电路包括多个电路块; 在集成电路内布线的全局控制信号; 和多个功率控制块。 每个功率控制块耦合到多个电路块的相应电路块，并且具有耦合以接收参考电压的第一输入和耦合以接收全局控制信号的第二输入。 对于每个电路块，全局控制信号使得参考电压与对应的电路块的耦合。 还公开了一种控制集成电路内的功率的方法。

公开(公告)号：US09268901B1

公开(公告)日：2016-02-23

申请号：US14452840

申请日：2014-08-06

Applicant: Xilinx, Inc.

Inventor： Santosh Kumar Sood

IPC: H03K19/177 ,  G06F17/50

CPC classification number: G06F17/5027 ,  G06F1/3287 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5081 ,  H03K19/17744 ,  H03K19/1776 ,  H03K19/17772

Abstract: Emulating power gating includes identifying an isolation circuit having a first input coupled to an output of a first power domain, a second input coupled to an isolation signal, and an output coupled to an input of a second power domain; removing a power gate circuit configured to selectively decouple the first power domain from a power supply responsive to a power gate signal; and decoupling the first input of the isolation circuit from the output of the first power domain. A power gate emulation circuit is inserted using a processor. The power gate emulation circuit is coupled to the isolation signal, the power gate signal, and the output of the first power domain.

Abstract translation: 模拟功率选通包括识别具有耦合到第一功率域的输出的第一输入，耦合到隔离信号的第二输入和耦合到第二功率域的输入的输出的隔离电路; 去除功率门电路，其被配置为响应于功率门信号而选择性地将第一功率域与电源分离; 以及将隔离电路的第一输入与第一功率域的输出去耦。 使用处理器插入电源门仿真电路。 电源门仿真电路耦合到隔离信号，功率门信号和第一功率域的输出。

公开(公告)号：US09606572B2

公开(公告)日：2017-03-28

申请号：US14503845

申请日：2014-10-01

Applicant: Xilinx, Inc.

Inventor： Santosh Kumar Sood

IPC: G06F1/08

CPC classification number: G06F1/08 ,  G06F1/12

Abstract: A circuit for processing data in an integrated circuit device comprises a selection circuit; a first register coupled to a first output of the selection circuit; a second register implemented as a latch and coupled to a second output of the selection circuit; and a signal line coupled between the output of the first register and an input of the selection circuit. The selection circuit enables the coupling of an output signal of the first register to an input of the second register. A method of processing data in an integrated circuit device is also disclosed.

公开(公告)号：US09337841B1

公开(公告)日：2016-05-10

申请号：US14507260

申请日：2014-10-06

Applicant: Xilinx, Inc.

Inventor： Santosh Kumar Sood

IPC: H03L5/00 ,  H03K19/0185

CPC classification number: H03K19/0185 ,  H03K3/011 ,  H03K19/018507

Abstract: A circuit for providing voltage level shifting in an integrated circuit includes an inverter having an input coupled to receive an input signal having a first voltage level; an output stage having a first transistor coupled in series with a second transistor, and an output node between the first transistor and the second transistor generating an output signal having a second voltage level. A gate of the second transistor is coupled to an output of the inverter. A pull-up transistor is coupled between a reference voltage having the second voltage level and a gate of the first transistor. A switch is coupled between the gate of the first transistor and the gate of the second transistor to control a voltage at the gate of the first transistor. A method of providing voltage level shifting in an integrated circuit is also disclosed.

Abstract translation: 用于在集成电路中提供电压电平移位的电路包括具有耦合以接收具有第一电压电平的输入信号的输入的反相器; 输出级具有与第二晶体管串联耦合的第一晶体管，以及在第一晶体管和第二晶体管之间的输出节点，其产生具有第二电压电平的输出信号。 第二晶体管的栅极耦合到反相器的输出端。 上拉晶体管耦合在具有第二电压电平的参考电压和第一晶体管的栅极之间。 开关耦合在第一晶体管的栅极和第二晶体管的栅极之间，以控制第一晶体管的栅极处的电压。 还公开了一种在集成电路中提供电压电平移位的方法。

公开(公告)号：US09246492B1

公开(公告)日：2016-01-26

申请号：US14749509

申请日：2015-06-24

Applicant: Xilinx, Inc.

Inventor： Santosh Kumar Sood

IPC: H03K19/0175 ,  H03K19/177

CPC classification number: H03K19/017581 ,  H03K19/17704

Abstract: In one example, a programmable integrated circuit (IC) includes a first logic tile in a first power domain having a first local voltage. The first logic tile includes a driver operable to use the first local voltage to output a signal having a logic-level referenced to the first local voltage. The first logic tile further includes a level-shifter coupled to receive the signal from the driver and operable to output a level-shifted signal having a logic-level referenced to a global handshaking voltage. The programmable IC further includes a second logic tile in a second power domain having a second local voltage, the second logic tile including a receiver operable to use the second local voltage to receive the level-shifted signal. The global handshaking voltage is at least as high as the first local voltage and at least as high as the second local voltage.

Abstract translation: 在一个示例中，可编程集成电路（IC）包括具有第一局部电压的第一功率域中的第一逻辑块。 第一逻辑瓦片包括可操作以使用第一局部电压输出具有参考第一局部电压的逻辑电平的信号的驱动器。 第一逻辑瓦片还包括电平移位器，其被耦合以从驱动器接收信号并且可操作以输出具有参考全局握手电压的逻辑电平的电平移位信号。 可编程IC还包括具有第二局部电压的第二功率域中的第二逻辑瓦片，第二逻辑瓦片包括可操作以使用第二局部电压来接收电平移位信号的接收器。 全局握手电压至少与第一局部电压一样高，并且至少与第二局部电压一样高。

公开(公告)号：US09054684B1

公开(公告)日：2015-06-09

申请号：US13848689

申请日：2013-03-21

Applicant: Xilinx, Inc.

Inventor： Santosh Kumar Sood ,  Praful Jain ,  Ramakrishna K. Tanikella

IPC: H03K5/125 ,  G01R31/3181

CPC classification number: H03K5/125 ,  G01R31/31816 ,  G01R31/318519

Abstract: A circuit block within an integrated circuit includes a multiplexor (225, 625) configured to pass either a first signal or a second signal, wherein the first signal is independent of the second signal. The circuit block further includes a first flip-flop (210, 610) configured to receive an output of the multiplexor and a second flip-flop (215, 615) configured to receive the second signal. In a first mode of operation, the multiplexor passes the first signal to the first flip-flop. Further, the first flip flop and the second flip-flop operate independently of one another. In a second mode of operation, the multiplexor passes the second signal to the first flip-flop. Further, the first flip-flop and the second flip-flop both receive the second signal.

Abstract translation: 集成电路内的电路块包括经配置以通过第一信号或第二信号的多路复用器（225,625），其中第一信号独立于第二信号。 电路块还包括被配置为接收多路复用器的输出的第一触发器（210,610）和被配置为接收第二信号的第二触发器（215,615）。 在第一操作模式中，多路复用器将第一信号传递到第一触发器。 此外，第一触发器和第二触发器彼此独立地操作。 在第二操作模式中，多路复用器将第二信号传递到第一触发器。 此外，第一触发器和第二触发器都接收第二信号。