公开(公告)号：US10062454B1

公开(公告)日：2018-08-28

申请号：US15372301

申请日：2016-12-07

Applicant: Xilinx, Inc.

Inventor： Ushasri Merugu ,  Mahesh Sankroj ,  Sudheer K. Koppolu ,  Siva V. N. Hemasunder Tallury

IPC: G11C29/52 ,  G06F1/12

CPC classification number: G11C29/52 ,  G06F1/12 ,  G11C7/222 ,  G11C29/023

Abstract: Disclosed approaches for probing signals in a plurality of clock domains include inputting unsynchronized trigger signals from the plurality of clock domains to a plurality of instances of a multi-synchronizer circuit, respectively. Each instance of the multi-synchronizer circuit includes a plurality of synchronizer circuits. One or more of the plurality of synchronizer circuits synchronizes the respective unsynchronized trigger signal with one clock signal from the plurality of clock domains. Output of one of the one or more synchronizer circuits in each instance of the multi-synchronizer circuit is selected as a respective synchronized trigger signal. A trigger equation is evaluated based on a state of each respective synchronized trigger signal. A final trigger signal is generated based the evaluating of the trigger equation, a trigger marker is stored in a memory in response to a state of the final trigger signal, and states of probed signals are stored in the memory.