公开(公告)号：US10816598B1

公开(公告)日：2020-10-27

申请号：US16148371

申请日：2018-10-01

Applicant: Xilinx, Inc.

Inventor： Ushasri Merugu ,  Mahesh Sankroj ,  Sharat Babu Kotamraju

IPC: G01R31/317 ,  G06F1/08 ,  G01R31/3177

Abstract: A system for debugging circuits includes an integrated circuit configured to implement a circuit under test and a logic analyzer controller coupled to the circuit under test. The system includes a host computing system configured to communicate with the logic analyzer controller and provide a debug command to the logic analyzer controller. The logic analyzer controller, in response to the debug command, controls operation of the circuit under test.

公开(公告)号：US10067189B1

公开(公告)日：2018-09-04

申请号：US15464217

申请日：2017-03-20

Applicant: Xilinx, Inc.

Inventor： Banadappa V. Shivaray ,  Ahmad R. Ansari ,  Sanjeeva R. Duggampudi ,  Pramod Surathkal ,  Ushasri Merugu ,  Bommana S. Rao ,  Sowmya Sheela Thati ,  Shashidhar S. Krishnamurthy

IPC: G01R31/3185 ,  G01R31/3177 ,  G01R31/317

Abstract: Disclosed circuitry includes input-output pads, receive flip-flops, and transmit flip-flops coupled to the input-output pads. Data path control circuitry is coupled to data path control flip-flops, the receive flip-flops and the transmit flip-flops. The data path control circuitry is configured to selectably couple the receive flip-flops and the transmit flip-flops to the input-output pads in response to states of the data path control flip-flops. Clock control circuitry is coupled to clock control flip-flops, the receive flip-flops and the transmit flip-flops. The clock control circuitry is configured to selectably apply one of multiple clock signals to the receive flip-flops and the transmit flip-flops in response to states of the clock control flip-flops. A first scan chain is coupled to the clock control flip-flops and the data path control flip-flops. A second scan chain is coupled to the receive flip-flops and the transmit flip-flops.

公开(公告)号：US10062454B1

公开(公告)日：2018-08-28

申请号：US15372301

申请日：2016-12-07

Applicant: Xilinx, Inc.

Inventor： Ushasri Merugu ,  Mahesh Sankroj ,  Sudheer K. Koppolu ,  Siva V. N. Hemasunder Tallury

IPC: G11C29/52 ,  G06F1/12

CPC classification number: G11C29/52 ,  G06F1/12 ,  G11C7/222 ,  G11C29/023

Abstract: Disclosed approaches for probing signals in a plurality of clock domains include inputting unsynchronized trigger signals from the plurality of clock domains to a plurality of instances of a multi-synchronizer circuit, respectively. Each instance of the multi-synchronizer circuit includes a plurality of synchronizer circuits. One or more of the plurality of synchronizer circuits synchronizes the respective unsynchronized trigger signal with one clock signal from the plurality of clock domains. Output of one of the one or more synchronizer circuits in each instance of the multi-synchronizer circuit is selected as a respective synchronized trigger signal. A trigger equation is evaluated based on a state of each respective synchronized trigger signal. A final trigger signal is generated based the evaluating of the trigger equation, a trigger marker is stored in a memory in response to a state of the final trigger signal, and states of probed signals are stored in the memory.