公开(公告)号：US10819680B1

公开(公告)日：2020-10-27

申请号：US15915981

申请日：2018-03-08

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Umang Parekh ,  Jeffrey H. Seltzer ,  Khang K. Dao ,  Kyle Corbett

IPC: H04L29/06 ,  G06F13/42

Abstract: System and method generally relate to protection of a bussed network. In such a system, an access controller is configured for bussed communication via a communication bus to obtain a current transaction. An interface firewall is coupled for bussed communication with the access controller and configured to check for a fault associated with a transfer. A data processing device is coupled for communication with the interface firewall and configured to execute the current transaction to provide the transfer for the interface firewall. The interface firewall is configured to detect the fault associated with the transfer, to block access to the data processing device associated with the fault, and to communicate a blocked status for the data processing device.

公开(公告)号：US09811618B1

公开(公告)日：2017-11-07

申请号：US13788189

申请日：2013-03-07

Applicant: Xilinx, Inc.

Inventor： Umang Parekh ,  Arvind Sundararajan ,  Sandeep Dutta

IPC: G06F17/50 ,  G06F15/78

CPC classification number: G06F17/5036 ,  G06F15/7867 ,  G06F17/5054

Abstract: A method is provided for simulating a program executable by a processor and a circuit design configured to communicate with the processor. A processor on a programmable IC is configured to execute the program. Programmable resources on the programmable IC are configured to implement a plurality of interface circuits. Each of the interface circuits is configured to communicate data between the processor and a simulation environment using a respective communication protocol. The interface circuits that uses a communication protocol used by the circuit design is enabled and other ones of the interface circuits are disabled. The circuit design is simulated in a simulation environment coupled to the programmable IC. During the simulating, the program is executed on the processor and data is communicated between the processor and the computing platform using the determined one of the plurality of interface circuits.