公开(公告)号：US09846587B1

公开(公告)日：2017-12-19

申请号：US14278263

申请日：2014-05-15

Applicant: Xilinx, Inc.

Inventor： Paul R. Schumacher ,  Graham F. Schelle ,  Patrick Lysaght ,  Yi-Hua Yang

IPC: G06F9/455

CPC classification number: G06F9/455 ,  G06F11/34 ,  G06F17/50

Abstract: A system includes a host data processing system and a target platform coupled to the host data processing system. The target platform includes an emulation system. The emulation system includes a processor system, an emulation circuit coupled to the processor system through an integrated circuit (IC) interconnect, and a performance monitor coupled to the IC interconnect. The emulation system receives, from the host data processing system, a software emulation model and a data traffic pattern. The emulation system emulates a system architecture by executing the software emulation model within the processor system and implementing the data traffic pattern over the IC interconnect using the emulation circuit. The emulation system provides, to the host data processing system, measurement data collected by the performance monitor during the emulation.

公开(公告)号：US09652410B1

公开(公告)日：2017-05-16

申请号：US14278470

申请日：2014-05-15

Applicant: Xilinx, Inc.

Inventor： Graham F. Schelle ,  Paul R. Schumacher ,  Patrick Lysaght ,  Yi-Hua Yang ,  Anthony Brandon

IPC: G06F9/44 ,  H03K19/177 ,  G06F13/10

CPC classification number: G06F13/10 ,  G06F9/44 ,  H03K19/17756

Abstract: Automated modification of configuration settings for an IC (IC) includes receiving, within a data processing system, desired data for a configuration setting of an IC, reading stored data for the configuration setting. A determination is made using the data processing system that the configuration setting is static and that the stored data differs from the desired data. Responsive to the determination, configuration data including the desired data is provided from the data processing system to the IC. At least a portion of a boot process of the IC is automatically initiated, wherein the boot process uses the configuration data.

公开(公告)号：US09348619B1

公开(公告)日：2016-05-24

申请号：US13797721

申请日：2013-03-12

Applicant: Xilinx, Inc.

Inventor： Patrick Lysaght ,  Paul R. Schumacher ,  Graham F. Schelle ,  Yi-Hua Yang

IPC: G06G7/62 ,  G06F9/455

CPC classification number: G06F9/455 ,  G06F17/5027

Abstract: A user interface is provided for selection of a previously specified scenario from a plurality of previously specified scenarios. Each previously specified scenario includes a previously specified topology of the electronic system, one or more previously specified parameter values applied to the electronic system, a previously specified traffic profile, and respective precompiled values of one or more measurands. In response to user selection of one of the previously specified scenarios, the precompiled values of the measurands are displayed. The user interface further provides for specification of a scenario. In response to user specification of a scenario, traffic emulation circuitry in the programmable IC is configured to execute the scenario. The value of the at least one measurand is computed and displayed.

Abstract translation: 提供用户界面用于从多个先前指定的场景中选择先前指定的场景。 每个先前指定的方案包括电子系统的先前指定的拓扑，应用于电子系统的一个或多个先前指定的参数值，先前指定的流量简档，以及一个或多个被测量的相应预编译值。 响应于用户选择之前指定的方案之一，显示被测量的预编译值。 用户界面还提供了场景的规范。 响应于场景的用户指定，可编程IC中的业务仿真电路被配置为执行该场景。 计算并显示至少一个被测量的值。

公开(公告)号：US09110524B1

公开(公告)日：2015-08-18

申请号：US14299736

申请日：2014-06-09

Applicant: Xilinx, Inc.

Inventor： Weirong Jiang ,  Gordon J. Brebner ,  Yi-Hua Yang

IPC: H03K19/173 ,  G06F1/04 ,  G05B19/045

CPC classification number: G06F1/04 ,  G05B19/045 ,  G05B2219/23289 ,  G06F1/10

Abstract: In an FSM circuit, look-ahead-cascade modules are coupled to receive possible states and corresponding subsets of data inputs. Merge modules are coupled to a second-to-the-lowest to highest order of the look-ahead-cascade modules. The second-to-the-lowest to highest order of disambiguation modules are coupled to at least a portion of the merge modules. The lowest order of the disambiguation modules is coupled to the lowest order of the look-ahead-cascade modules. The lowest-to-highest order of the disambiguation modules are coupled to receive respective sets of interim states of rN states each to select respective sets of next states of r states each. A state register is coupled to receive a portion of the highest order of the sets of next states to provide a select signal. Each of the disambiguation modules is coupled to receive the select signal for selection of the sets of next states of the r states each.

Abstract translation: 在FSM电路中，先行级联模块被耦合以接收可能的状态和相应的数据输入子集。 合并模块耦合到先行级联模块的第二到最低级别。 消歧模块的第二到最低到最高顺序耦合到合并模块的至少一部分。 消歧模块的最低顺序与先行级联模块的最低级联联。 消歧模块的最低到最高顺序被耦合以接收各自的rN状态的各个中间状态集合，以各自选择各状态的下一个状态。 状态寄存器被耦合以接收下一状态组的最高阶的一部分以提供选择信号。 每个消歧模块被耦合以接收选择信号，用于选择各状态的下一个状态的集合。