公开(公告)号：US20230259627A1

公开(公告)日：2023-08-17

申请号：US17651030

申请日：2022-02-14

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Yu Liu ,  Yenpang Lin ,  Lizhi Hou ,  Cheng Zhen ,  Yidong Zhang

IPC: G06F21/57 ,  G06F21/64 ,  G06F21/71 ,  G06F13/16

CPC classification number: G06F21/572 ,  G06F21/64 ,  G06F21/71 ,  G06F13/1642 ,  G06F13/1663

Abstract: An integrated circuit can include a communication endpoint configured to maintain a communication link with a host computer, a queue configured to receive a plurality of host commands from the host computer via the communication link, and a processor configured to execute a device runtime. The processor, responsive to executing the device runtime, is configured to perform validation of the host commands read from the queue and selectively execute the host commands based on a result of the validation on a per host command basis. The host commands are executable by the processor to manage functions of the integrated circuit. The queue is implemented in a region of memory that is shared by the integrated circuit and the host computer.

公开(公告)号：US11861010B2

公开(公告)日：2024-01-02

申请号：US17651030

申请日：2022-02-14

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Yu Liu ,  Yenpang Lin ,  Lizhi Hou ,  Cheng Zhen ,  Yidong Zhang

IPC: G06F21/64 ,  G06F21/71 ,  G06F21/57 ,  G06F13/16

CPC classification number: G06F21/572 ,  G06F13/1642 ,  G06F13/1663 ,  G06F21/64 ,  G06F21/71

Abstract: An integrated circuit can include a communication endpoint configured to maintain a communication link with a host computer, a queue configured to receive a plurality of host commands from the host computer via the communication link, and a processor configured to execute a device runtime. The processor, responsive to executing the device runtime, is configured to perform validation of the host commands read from the queue and selectively execute the host commands based on a result of the validation on a per host command basis. The host commands are executable by the processor to manage functions of the integrated circuit. The queue is implemented in a region of memory that is shared by the integrated circuit and the host computer.