公开(公告)号：US20240088900A1

公开(公告)日：2024-03-14

申请号：US18509128

申请日：2023-11-14

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Tim Tuan ,  Javier Cabezas Rodriguez ,  David Clarke ,  Peter McColgan ,  Zachary Blaise Dickman ,  Saurabh Mathur ,  Amarnath Kasibhatla ,  Francisco Barat Quesada

IPC: H03K19/1776 ,  G11C5/02 ,  H03K19/17764 ,  H03K19/17784

CPC classification number: H03K19/1776 ,  G11C5/025 ,  H03K19/17764 ,  H03K19/17784

Abstract: An apparatus includes a data processing array having a plurality of array tiles. The plurality of array tiles include a plurality of compute tiles. The compute tiles include a core coupled to a random-access memory (RAM) in a same compute tile and to a RAM of at least one other compute tile. The data processing array is subdivided into a plurality of partitions. Each partition includes a plurality of array tiles including at least one of the plurality of compute tiles. The apparatus includes a plurality of clock gate circuits being programmable to selectively gate a clock signal provided to a respective one of the plurality of partitions.

公开(公告)号：US20230336179A1

公开(公告)日：2023-10-19

申请号：US17659423

申请日：2022-04-15

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Tim Tuan ,  Javier Cabezas Rodriguez ,  David Clarke ,  Peter McColgan ,  Zachary Blaise Dickman ,  Saurabh Mathur ,  Amarnath Kasibhatla ,  Francisco Barat Quesada

IPC: H03K19/1776 ,  H03K19/17784 ,  H03K19/17764 ,  G11C5/02

CPC classification number: H03K19/1776 ,  H03K19/17784 ,  H03K19/17764 ,  G11C5/025

Abstract: An apparatus includes a data processing array having a plurality of array tiles. Each array tile can include a random-access memory (RAM) having a local memory interface accessible by circuitry within the array tile and an adjacent memory interface accessible by circuitry disposed within an adjacent array tile. Each adjacent memory interface of each array tile can include isolation logic that is programmable to allow the circuitry disposed within the adjacent array tile to access the RAM or prevent the circuitry disposed within the adjacent array tile from accessing the RAM. The data processing array can be subdivided into a plurality of partitions wherein the isolation logic of the adjacent memory interfaces is programmed to prevent array tiles from accessing RAMs across a boundary between the plurality of partitions.

公开(公告)号：US11669464B1

公开(公告)日：2023-06-06

申请号：US16858417

申请日：2020-04-24

Applicant: XILINX, INC.

Inventor： Goran Hk Bilski ,  Baris Ozgul ,  David Clarke ,  Juan J. Noguera Serra ,  Jan Langer ,  Zachary Dickman ,  Sneha Bhalchandra Date ,  Tim Tuan

IPC: G06F12/1081 ,  G06F12/06 ,  G06F9/52 ,  G06F15/78 ,  G06F12/02

CPC classification number: G06F12/1081 ,  G06F9/524 ,  G06F12/0246 ,  G06F12/0607 ,  G06F15/7807

Abstract: Examples herein describe performing non-sequential DMA read and writes. Rather than storing data sequentially, a DMA engine can write data into memory using non-sequential memory addresses. A data processing engine (DPE) controller can submit a first job using first parameters that instruct the DMA engine to store data using a first non-sequential write pattern. The DPE controller can also submit a second job using second parameters that instruct the DMA engine to store data using a second, different non-sequential write pattern. In this manner, the DMA engine can switch to performing DMA writes using different non-sequential patterns. Similarly, the DMA engine can use non-sequential reads to retrieve data from memory. When performing a first DMA read, the DMA engine can retrieve data from memory using a first sequential pattern and then perform a second DMA read where data is retrieved from memory using a second non-sequential read pattern.

公开(公告)号：US11336287B1

公开(公告)日：2022-05-17

申请号：US17196574

申请日：2021-03-09

Applicant: Xilinx, Inc.

Inventor： Javier Cabezas Rodriguez ,  Juan J. Noguera Serra ,  David Clarke ,  Sneha Bhalchandra Date ,  Tim Tuan ,  Peter McColgan ,  Jan Langer ,  Baris Ozgul

IPC: H03K19/1776 ,  H03K19/17704 ,  H03K19/17768 ,  H03K19/17758 ,  H03K19/17796

Abstract: An integrated circuit can include a data processing engine (DPE) array having a plurality of tiles. The plurality of tiles can include a plurality of DPE tiles, wherein each DPE tile includes a stream switch, a core configured to perform operations, and a memory module. The plurality of tiles can include a plurality of memory tiles, wherein each memory tile includes a stream switch, a direct memory access (DMA) engine, and a random-access memory. The DMA engine of each memory tile may be configured to access the random-access memory within the same memory tile and the random-access memory of at least one other memory tile. Selected ones of the plurality of DPE tiles may be configured to access selected ones of the plurality of memory tiles via the stream switches.

公开(公告)号：US20190303347A1

公开(公告)日：2019-10-03

申请号：US15944408

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Goran H.K. Bilski ,  Juan J. Noguera Serra ,  Baris Ozgul ,  Jan Langer ,  David Clarke ,  Sneha Bhalchandra Date

IPC: G06F15/80

Abstract: An example data processing engine (DPE) for a DPE array in an integrated circuit (IC) includes: a core; a memory including a data memory and a program memory, the program memory coupled to the core, the data memory coupled to the core and including at least one connection to a respective at least one additional core external to the DPE; support circuitry including hardware synchronization circuitry and direct memory access (DMA) circuitry each coupled to the data memory; streaming interconnect coupled to the DMA circuitry and the core; and memory-mapped interconnect coupled to the core, the memory, and the support circuitry.

公开(公告)号：US20190303328A1

公开(公告)日：2019-10-03

申请号：US15944617

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Goran H.K. Balski ,  Juan J. Noguera Serra ,  David Clarke ,  Tim Tuan ,  Peter McColgan ,  Zachary Dickman ,  Baris Ozgul ,  Jan Langer

IPC: G06F13/40 ,  G06F13/16

Abstract: A device may include a plurality of data processing engines, a subsystem, and an SoC interface block coupled to the plurality of data processing engines and the subsystem. The SoC interface block may be configured to exchange data between the subsystem and the plurality of data processing engines.

公开(公告)号：US11848670B2

公开(公告)日：2023-12-19

申请号：US17659423

申请日：2022-04-15

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Tim Tuan ,  Javier Cabezas Rodriguez ,  David Clarke ,  Peter McColgan ,  Zachary Blaise Dickman ,  Saurabh Mathur ,  Amarnath Kasibhatla ,  Francisco Barat Quesada

IPC: H03K19/1776 ,  G11C5/02 ,  H03K19/17764 ,  H03K19/17784

CPC classification number: H03K19/1776 ,  G11C5/025 ,  H03K19/17764 ,  H03K19/17784

Abstract: An apparatus includes a data processing array having a plurality of array tiles. Each array tile can include a random-access memory (RAM) having a local memory interface accessible by circuitry within the array tile and an adjacent memory interface accessible by circuitry disposed within an adjacent array tile. Each adjacent memory interface of each array tile can include isolation logic that is programmable to allow the circuitry disposed within the adjacent array tile to access the RAM or prevent the circuitry disposed within the adjacent array tile from accessing the RAM. The data processing array can be subdivided into a plurality of partitions wherein the isolation logic of the adjacent memory interfaces is programmed to prevent array tiles from accessing RAMs across a boundary between the plurality of partitions.

公开(公告)号：US20230131698A1

公开(公告)日：2023-04-27

申请号：US18145810

申请日：2022-12-22

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Goran HK Bilski ,  Jan Langer ,  Baris Ozgul ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Tim Tuan ,  David Clarke

IPC: G06F3/06 ,  G06F15/78 ,  G06F15/173

Abstract: A device includes a data processing engine array having a plurality of data processing engines organized in a grid having a plurality of rows and a plurality of columns. Each data processing engine includes a core, a memory module including a memory and a direct memory access engine. Each data processing engine includes a stream switch connected to the core, the direct memory access engine, and the stream switch of one or more adjacent data processing engines. Each memory module includes a first memory interface directly coupled to the core in the same data processing engine and one or more second memory interfaces directly coupled to the core of each of the one or more adjacent data processing engines.

公开(公告)号：US20230057903A1

公开(公告)日：2023-02-23

申请号：US17819872

申请日：2022-08-15

Applicant: Xilinx, Inc.

Inventor： David Clarke ,  Juan J. Noguera Serra ,  Javier Cabezas Rodriguez ,  Zachary Blaise Dickman ,  Pedro Miguel Parola Duarte ,  Jose Marques

IPC: G06F9/445 ,  G06F9/50

Abstract: An integrated circuit includes a data processing array. The data processing array includes a plurality of compute tiles each having a processor. The integrated circuit includes an array controller coupled to the data processing array. The array controller is adapted to configure the plurality of compute tiles of the data processing array to implement an application. The application specifies kernels executable by the processors and stream channels that convey data to the plurality of compute tiles. The array controller is configured to initiate execution of workloads by the data processing array as configured with the application.

公开(公告)号：US11323391B1

公开(公告)日：2022-05-03

申请号：US16833029

申请日：2020-03-27

Applicant: XILINX, INC.

Inventor： Peter McColgan ,  David Clarke ,  Goran Hk Bilski ,  Juan J. Noguera Serra ,  Baris Ozgul ,  Jan Langer ,  Tim Tuan

IPC: H04L12/935 ,  G06F13/28 ,  H04L49/00

Abstract: Some examples described herein relate to multi-port stream switches of data processing engines (DPEs) of an electronic device, such as a programmable device. In an example, a programmable device includes a plurality of DPEs. Each DPE of the DPEs includes a hardened processor core and a stream switch. The stream switch is connected to respective stream switches of ones of the DPEs that neighbor the respective DPE in respective ones of directions. The stream switch has input ports associated with each direction of the directions and has output ports associated with each direction of the directions. For each direction of the directions, each input port of the input ports associated with the respective direction is selectively connectable to one of the output ports associated with the respective direction.