摘要:
Systems and devices for ripple reduction in a DC/DC converter are presented. The disclosed systems and methods enable ripple reduction in discontinuous conduction mode (DCM) operation. In DCM, the inductor current peak to peak ripple may be reduced based on the load current. To achieve the reduction of the inductor peak to peak current ripple, a digital counter is used to count the time between consecutive PWM pulses. The digital output of the counter is used to control the pulse width modulation. As the digital output of the counter increases, the PWM on-time decreases. Since the PWM pulse is demanded by the load in DCM mode, the peak to peak inductor ripple is modulated by the counter, or, in turn, modulated by the load current.
摘要:
Systems and devices for smooth light load operation in a DC/DC converter are presented. The disclosed systems and methods enable smooth discontinuous conduction mode (DCM)/continuous conduction mode (CCM) transition. The disclosed systems and methods of smooth light load operation in a DC/DC converter may also avoid the generation of sub-harmonics during light load operation. In an example embodiment, a rising ramp is used to control the ON time of the converter oscillator, while a falling ramp controls the OFF time. During DCM operation, the minimum value of the falling ramp is clamped. The clamping of the falling ramp ensures a substantially similar level of the error amplifier output in both CCM and DCM and avoids disturbances caused by a difference in the error amplifier outputs between the modes.
摘要:
Systems and devices for smooth light load operation in a DC/DC converter are presented. The disclosed systems and methods enable smooth discontinuous conduction mode (DCM)/continuous conduction mode (CCM) transition. The disclosed systems and methods of smooth light load operation in a DC/DC converter may also avoid the generation of sub-harmonics during light load operation. In an example embodiment, a rising ramp is used to control the ON time of the converter oscillator, while a falling ramp controls the OFF time. During DCM operation, the minimum value of the falling ramp is clamped. The clamping of the falling ramp ensures a substantially similar level of the error amplifier output in both CCM and DCM and avoids disturbances caused by a difference in the error amplifier outputs between the modes.
摘要:
Systems and devices for ripple reduction in a DC/DC converter are presented. The disclosed systems and methods enable ripple reduction in discontinuous conduction mode (DCM) operation. In DCM, the inductor current peak to peak ripple may be reduced based on the load current. To achieve the reduction of the inductor peak to peak current ripple, a digital counter is used to count the time between consecutive PWM pulses. The digital output of the counter is used to control the pulse width modulation. As the digital output of the counter increases, the PWM on-time decreases. Since the PWM pulse is demanded by the load in DCM mode, the peak to peak inductor ripple is modulated by the counter, or, in turn, modulated by the load current.
摘要:
A buck converter with an asymmetric threshold voltage of its gate drive circuit design for improving power efficiency while keeping the gate drive design simple.
摘要:
A multiphase buck converter that includes smart two-phase power stages for reducing switching losses. Each of the smart power stages includes a first high side switch, a second high side switch, a first low side switch, a second low side switch, a switching capacitor, a first inductor, and a second inductor. The exemplary multiphase buck converter includes two such smart power stages and a multiphase controller for generating PWM signals for driving the two smart power stages synchronously.
摘要:
A multiphase converter comprising a plurality of converter circuits, each converter circuit having series connected high and low side switches connected across a voltage bus with a common node provided therebetween, each of the common nodes connected through a respective inductor to an output node of the converter coupled to a load, the high and low side switches each being controlled by a control circuit to provide a desired output voltage at the output node, the control circuit including a first circuit for disabling and enabling at least one phase in response to a condition of the load, the circuit causing the high side switch to be turned on prior to the lower side switch when a disabled phase is enabled.
摘要:
A control circuit for use in controlling a phase of a multi-phase voltage converter in accordance with an embodiment of the present invention includes a driver operable to provide a first control signal to a high side switch of a half-bridge of the phase and a second control signal to a low side switch of the half bridge, such that a desired output voltage is provided by the phase, current sensing circuitry operable to detect the output current of the phase, a comparator operable to compare the output current to a threshold current value and a disabling device operable to provide an enable/disable signal to disable the driver when the output current is below the threshold current value.
摘要:
A multi-phase converter comprising 2N+1 inductors; and 2N+1 switching converters parallel connected and each including a switched node; wherein N is an even integer, a pair of said inductors are coupled and wound about a common core and each said coupled inductor is connected at one pole thereof to a respective switched node and at another pole thereof to an output node, and at least one of said inductors is uncoupled from the other inductors.
摘要:
A pulse width modulation control circuit for providing a pulse width modulation signal in accordance with an embodiment of the present application includes a comparator operable to compare a first input to a second input and to provide the pulse width modulation signal based on the comparison, wherein the first input is an error signal and the second input is a ramp signal, wherein a first portion of the ramp is a decreasing ramp signal having a first slew rate and a second portion of the ramp signal is an increasing ramp signal having a second slew rate.