公开(公告)号：US20240235570A9

公开(公告)日：2024-07-11

申请号：US17971801

申请日：2022-10-24

申请人： YUAN-JU CHAO

发明人： YUAN-JU CHAO

IPC分类号： H03M1/12

CPC分类号： H03M1/1245

摘要： A method of eliminating reference voltage of Analog-to-Digital Converter to enhance faster conversion rate, achieve compact size and decrease power consumption for Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC).

公开(公告)号：US20240235565A1

公开(公告)日：2024-07-11

申请号：US18407613

申请日：2024-01-09

申请人： YUAN-JU CHAO ,  JOHN H YU ,  KRISHNAMURTHY SUBRAMANIAN

发明人： YUAN-JU CHAO ,  JOHN H YU ,  KRISHNAMURTHY SUBRAMANIAN

IPC分类号： H03M1/06

CPC分类号： H03M1/0604

摘要： A charge-injection SAR ADC device has a modified charge-injection cell (CIC), and a complementary to absolute temperature (CTAT) circuit for generating a bias voltage. The CIC and CTAT circuits cooperate to correct for process, voltage, and temperature (PVT) variation that affect SAR ADC input full scale. The CIC has been modified to have transistors that are in a cascoded relationship with transistors operating to maintain a reservoir of charge. The CTAT circuit is designed to substantially replicate the CIC, and it tracks the CIC operation to correct variations in transistor threshold voltage due to variations in PVT.

公开(公告)号：US20180331689A1

公开(公告)日：2018-11-15

申请号：US15653156

申请日：2017-07-18

申请人： YUAN-JU CHAO ,  TA-SHUN CHU

发明人： YUAN-JU CHAO ,  TA-SHUN CHU

IPC分类号： H03M1/06 ,  H03M1/10 ,  H03K5/24 ,  H03K5/00 ,  H03M1/12 ,  H03M1/00

CPC分类号： H03K5/24 ,  H03K2005/00058 ,  H03M1/00 ,  H03M1/06 ,  H03M1/1071 ,  H03M1/12 ,  H03M1/125 ,  H03M1/468

摘要： A method of increasing SAR ADC conversion rate and reducing power consumption by employing a new timing scheme and minimizing timing delay for each bit-test during binary-search process. The high frequency clock input requirement is eliminated and higher speed rate can be achieved in SAR ADC.

公开(公告)号：US20240137036A1

公开(公告)日：2024-04-25

申请号：US17971801

申请日：2022-10-23

申请人： YUAN-JU CHAO

发明人： YUAN-JU CHAO

IPC分类号： H03M1/12

CPC分类号： H03M1/1245

摘要： A method of eliminating reference voltage of Analog-to-Digital Converter to enhance faster conversion rate, achieve compact size and decrease power consumption for Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC).

公开(公告)号：US20230148381A1

公开(公告)日：2023-05-11

申请号：US17521823

申请日：2021-11-08

申请人： YUAN-JU CHAO

发明人： YUAN-JU CHAO

IPC分类号： H03M1/06

CPC分类号： H03M1/0604

摘要： A method of expanding current steering Digital-to-Analog Converter (DAC) output amplitude and enhancing linearity performance. Level shifters with regulated supply and ground voltage are inserted before current source latches. Extra devices and small current are placed between switches and resistor load to enhance the linearity of current steering DAC.