公开(公告)号：US20130113516A1

公开(公告)日：2013-05-09

申请号：US13572143

申请日：2012-08-10

申请人： Yan-Bin LUO ,  Sheng-Ming CHANG ,  Bo-Wei HSIEH ,  Ming-Shi LIOU ,  Chih-Chien HUNG ,  Shang-Ping CHEN

发明人： Yan-Bin LUO ,  Sheng-Ming CHANG ,  Bo-Wei HSIEH ,  Ming-Shi LIOU ,  Chih-Chien HUNG ,  Shang-Ping CHEN

IPC分类号： H03K19/00

CPC分类号： H03K19/0005 ,  G11C7/10 ,  G11C7/1048 ,  G11C7/1072 ,  G11C11/4093

摘要： A termination circuit for a plurality of memories controlled by a controller is provided. The termination circuit includes a plurality of drivers, a plurality of resistors and a plurality of capacitors. Each of the drivers is coupled to the memories via a transmission line. Each of the resistors is coupled to the corresponding driver via the corresponding transmission line. Each of the capacitors is coupled between the corresponding resistor and a reference voltage. The controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers.

摘要翻译： 提供了一种由控制器控制的多个存储器的终端电路。 终端电路包括多个驱动器，多个电阻器和多个电容器。 每个驱动器经由传输线耦合到存储器。 每个电阻器经由相应的传输线耦合到相应的驱动器。 每个电容器耦合在相应的电阻器和参考电压之间。 控制器经由驱动器耦合到存储器，并且当经由对应于传输线的传输线传输到存储器的逻辑“0”和逻辑“1”的数量时，控制器向一个驱动器提供特定的代码 其中一个驱动器是不平衡的，以便调整与其中一个驱动器相对应的电容器的终端电压。

公开(公告)号：US20130088929A1

公开(公告)日：2013-04-11

申请号：US13617394

申请日：2012-09-14

申请人： Yan-Bin LUO ,  Chih-Chien HUNG ,  Qui-Ting CHEN ,  Shang-Ping CHEN

发明人： Yan-Bin LUO ,  Chih-Chien HUNG ,  Qui-Ting CHEN ,  Shang-Ping CHEN

IPC分类号： G11C7/10

CPC分类号： G06F13/16 ,  G06F1/3275 ,  G06F13/1668 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/06 ,  Y02D10/13 ,  Y02D10/14

摘要： A memory controller is provided. The memory controller is powered by first and second power source and includes an input/output pin, a driver circuit, a terminal resistor, and an input buffer. The driver circuit is coupled to the input/output pin and capable of providing to a writing signal to the input/output pin. The terminal resistor is coupled between the input/output pin and the first power source. The input buffer is coupled to the input/output pin and capable of receiving a reading signal from the input/output pin. No terminal resistor is coupled between the input/output pin and the second power source.

摘要翻译： 提供存储器控制器。 存储器控制器由第一和第二电源供电，并且包括输入/​​输出引脚，驱动器电路，终端电阻器和输入缓冲器。 驱动器电路耦合到输入/输出引脚，并且能够向输入/输出引脚提供写入信号。 端子电阻耦合在输入/输出引脚和第一个电源之间。 输入缓冲器耦合到输入/输出引脚，并能够从输入/输出引脚接收读取信号。 输入/输出引脚和第二个电源之间没有端子电阻耦合。

公开(公告)号：US20090129524A1

公开(公告)日：2009-05-21

申请号：US11940486

申请日：2007-11-15

申请人： Shang-Ping CHEN ,  Ping-Ying WANG

发明人： Shang-Ping CHEN ,  Ping-Ying WANG

IPC分类号： H03D3/24 ,  H04B1/69

CPC分类号： H03B19/00 ,  H03L7/081 ,  H03L7/1976

摘要： Spread spectrum clock generators. A phase lock loop generates an output clock according to a first input clock and a second input clock, a delay line is coupled between the first input clock and the phase lock loop. A modulation unit provides a modulation signal to control the delay line thereby modulating phase of the first input clock, such that frequency of the output clock generated by the phase lock loop varies periodically.

摘要翻译： 扩频时钟发生器。 锁相环根据第一输入时钟和第二输入时钟产生输出时钟，延迟线耦合在第一输入时钟和锁相环之间。 调制单元提供调制信号以控制延迟线，从而调制第一输入时钟的相位，使得由锁相环产生的输出时钟的频率周期性地变化。