公开(公告)号：US20130113516A1

公开(公告)日：2013-05-09

申请号：US13572143

申请日：2012-08-10

申请人： Yan-Bin LUO ,  Sheng-Ming CHANG ,  Bo-Wei HSIEH ,  Ming-Shi LIOU ,  Chih-Chien HUNG ,  Shang-Ping CHEN

发明人： Yan-Bin LUO ,  Sheng-Ming CHANG ,  Bo-Wei HSIEH ,  Ming-Shi LIOU ,  Chih-Chien HUNG ,  Shang-Ping CHEN

IPC分类号： H03K19/00

CPC分类号： H03K19/0005 ,  G11C7/10 ,  G11C7/1048 ,  G11C7/1072 ,  G11C11/4093

摘要： A termination circuit for a plurality of memories controlled by a controller is provided. The termination circuit includes a plurality of drivers, a plurality of resistors and a plurality of capacitors. Each of the drivers is coupled to the memories via a transmission line. Each of the resistors is coupled to the corresponding driver via the corresponding transmission line. Each of the capacitors is coupled between the corresponding resistor and a reference voltage. The controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers.

摘要翻译： 提供了一种由控制器控制的多个存储器的终端电路。 终端电路包括多个驱动器，多个电阻器和多个电容器。 每个驱动器经由传输线耦合到存储器。 每个电阻器经由相应的传输线耦合到相应的驱动器。 每个电容器耦合在相应的电阻器和参考电压之间。 控制器经由驱动器耦合到存储器，并且当经由对应于传输线的传输线传输到存储器的逻辑“0”和逻辑“1”的数量时，控制器向一个驱动器提供特定的代码 其中一个驱动器是不平衡的，以便调整与其中一个驱动器相对应的电容器的终端电压。

公开(公告)号：US08415979B2

公开(公告)日：2013-04-09

申请号：US12940033

申请日：2010-11-04

申请人： Kuan-Hua Chao ,  Yan-Bin Luo ,  Tse-Hsiang Hsu

发明人： Kuan-Hua Chao ,  Yan-Bin Luo ,  Tse-Hsiang Hsu

IPC分类号： H03K19/0175

CPC分类号： H03K19/018578 ,  H03K19/00384 ,  H04L25/0272 ,  H04L25/0278

摘要： A calibration circuit for calibrating a differential driver with a differential output port including a first output node and a second output node includes: a comparing circuit arranged to receive a first output voltage corresponding to the first output node and a second output voltage corresponding to the second output node, and generate a comparison result according to the first output voltage, the second output voltage, and a predetermined voltage; and a controlling circuit coupled to the comparing circuit, a first resistive element and a second resistive element. The controlling circuit is arranged to adjust the first resistive element and the second resistive element according to the comparison result, wherein the first resistive element is coupled between the first output node and a reference voltage, and the second resistive element is coupled between the second output node and the reference voltage.

摘要翻译： 一种用于利用包括第一输出节点和第二输出节点的差分输出端口来校准差分驱动器的校准电路包括：比较电路，被布置成接收对应于第一输出节点的第一输出电压和对应于第二输出节点的第二输出电压 输出节点，并根据第一输出电压，第二输出电压和预定电压产生比较结果; 以及耦合到所述比较电路的控制电路，第一电阻元件和第二电阻元件。 控制电路被布置成根据比较结果调整第一电阻元件和第二电阻元件，其中第一电阻元件耦合在第一输出节点和参考电压之间，并且第二电阻元件耦合在第二输出 节点和参考电压。

公开(公告)号：US20110043259A1

公开(公告)日：2011-02-24

申请号：US12917894

申请日：2010-11-02

申请人： Yan-Bin Luo ,  Tun-Shih Chen ,  Min-Chung Chou

发明人： Yan-Bin Luo ,  Tun-Shih Chen ,  Min-Chung Chou

IPC分类号： H03K3/00

CPC分类号： H03K19/018528 ,  H04L25/0272 ,  H04L25/028

摘要： A multifunctional output driver capable of transmitting signals of different interfaces in different modes is provided, in which first and second current sources are provided, and first to fourth switching devices are coupled between the first and second current sources, and the first and second current source and the first to the fourth switching devices act as a current steering circuit. In a first transmission mode, the first and second switching devices are turned off, and the third and fourth switching devices and the first current source act as a current mode logic circuit to provide an output signal compatible with a first transmission interface according to an input signal from a pre-driver. In a second transmission mode, the current steering circuit outputs an output signal compatible with a second transmission interface according to the input signal from the pre-driver.

摘要翻译： 提供能够以不同模式发送不同接口的信号的多功能输出驱动器，其中提供第一和第二电流源，并且第一至第四开关器件耦合在第一和第二电流源之间，第一和第二电流源 并且第一至第四开关装置用作电流转向电路。 在第一传输模式中，第一和第二开关器件被关断，并且第三和第四开关器件和第一电流源用作电流模式逻辑电路，以根据输入提供与第一传输接口兼容的输出信号 来自前驱动器的信号。 在第二传输模式中，当前转向电路根据来自预驱动器的输入信号输出与第二传输接口兼容的输出信号。

公开(公告)号：US20100118932A1

公开(公告)日：2010-05-13

申请号：US12269187

申请日：2008-11-12

申请人： Yan-Bin Luo ,  Tang-Hung Po

发明人： Yan-Bin Luo ,  Tang-Hung Po

IPC分类号： H04N7/26 ,  H04N5/38 ,  H04N7/01

CPC分类号： G09G3/2096 ,  G09G2370/14

摘要： Multifunctional transmitters capable of transmitting signals of different specifications in different modes are provided, in which N output units are provided and each output unit comprises a serializer and an output driver. A control unit, according to a mode selection signal, selects a first set of output units from the N output units to transmit a first video data compatible with a first transmission interface under a first transmission mode and selects a second set of output units from the first set of output units to transmit a second video data compatible with a second transmission interface which is different from the first transmission interface under a second transmission mode.

摘要翻译： 提供能够以不同模式传输不同规格信号的多功能发射机，其中提供N个输出单元，每个输出单元包括串行器和输出驱动器。 控制单元根据模式选择信号从N个输出单元中选择第一组输出单元，以在第一传输模式下发送与第一传输接口兼容的第一视频数据，并从第一传输模式中选择第二组输出单元 第一组输出单元，用于在第二传输模式下传输与第一传输接口不同的第二传输接口兼容的第二视频数据。

公开(公告)号：US20100111156A1

公开(公告)日：2010-05-06

申请号：US12426987

申请日：2009-04-21

申请人： Yan-Bin Luo ,  Qui-Ting Chen

发明人： Yan-Bin Luo ,  Qui-Ting Chen

IPC分类号： H03H7/40

CPC分类号： H03H11/1291 ,  H04L25/03885

摘要： A tunable equalizer with a tunable equalizer frequency response is provided. The tunable equalizer includes an amplifier circuit for amplifying input signals and a tunable circuit coupled to the amplifier circuit. The tunable circuit is arranged to provide a zero point in the equalizer frequency response and the zero point is adjusted according to a controllable value. When the controllable value varies according to a uniform offset, the corresponding zero point varies according to a non-uniform offset.

摘要翻译： 提供了具有可调均衡器频率响应的可调均衡器。 可调谐均衡器包括用于放大输入信号的放大器电路和耦合到放大器电路的可调谐电路。 可调电路被设置成在均衡器频率响应中提供零点，并且根据可控值调整零点。 当可控值根据均匀偏移而变化时，相应的零点根据不均匀的偏移而变化。

公开(公告)号：US08952718B2

公开(公告)日：2015-02-10

申请号：US13572143

申请日：2012-08-10

申请人： Yan-Bin Luo ,  Sheng-Ming Chang ,  Bo-Wei Hsieh ,  Ming-Shi Liou ,  Chih-Chien Hung ,  Shang-Ping Chen

发明人： Yan-Bin Luo ,  Sheng-Ming Chang ,  Bo-Wei Hsieh ,  Ming-Shi Liou ,  Chih-Chien Hung ,  Shang-Ping Chen

IPC分类号： H03K19/003 ,  H03K19/00 ,  G11C7/10 ,  G11C11/4093

CPC分类号： H03K19/0005 ,  G11C7/10 ,  G11C7/1048 ,  G11C7/1072 ,  G11C11/4093

摘要： A termination circuit for a plurality of memories controlled by a controller is provided. The termination circuit includes a plurality of drivers, a plurality of resistors and a plurality of capacitors. Each of the drivers is coupled to the memories via a transmission line. Each of the resistors is coupled to the corresponding driver via the corresponding transmission line. Each of the capacitors is coupled between the corresponding resistor and a reference voltage. The controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers.

摘要翻译： 提供了一种由控制器控制的多个存储器的终端电路。 终端电路包括多个驱动器，多个电阻器和多个电容器。 每个驱动器经由传输线耦合到存储器。 每个电阻器经由相应的传输线耦合到相应的驱动器。 每个电容器耦合在相应的电阻器和参考电压之间。 控制器经由驱动器耦合到存储器，并且当经由对应于传输线的传输线传输到存储器的逻辑“0”和逻辑“1”的数量时，控制器向一个驱动器提供特定的代码 其中一个驱动器是不平衡的，以便调整与其中一个驱动器相对应的电容器的终端电压。

公开(公告)号：US08665606B2

公开(公告)日：2014-03-04

申请号：US13041442

申请日：2011-03-07

申请人： Huai-Yuan Feng ,  Ching-Gu Pan ,  Yan-Bin Luo ,  Hua Wu ,  Shang-Yi Lin

发明人： Huai-Yuan Feng ,  Ching-Gu Pan ,  Yan-Bin Luo ,  Hua Wu ,  Shang-Yi Lin

IPC分类号： H05K1/11 ,  H05K1/14 ,  H05K1/02

CPC分类号： G06F17/5072 ,  H05K1/029 ,  H05K1/0295 ,  H05K2201/09954 ,  H05K2201/10189 ,  H05K2201/10689

摘要： An electronic device includes an integrated circuit, a connector, and a circuit board. The integrated circuit includes a first signal processing circuit, a second signal processing circuit, and an interface multiplexer having a first input port electrically connected to the first signal processing circuit, a second input port electrically connected to the second signal processing circuit, and an output port arranged to be electrically connected to the first input port or the second input port. The circuit board carries the integrated circuit and has a plurality of connector placement sites, including at least a first connector placement site each dedicated to the first signal processing circuit and at least a second connector placement site each dedicated to the second signal processing circuit. The connector placement sites and the output port of the interface multiplexer are electrically connected in series. The connector is installed on one of the connector placement sites.

摘要翻译： 电子设备包括集成电路，连接器和电路板。 集成电路包括第一信号处理电路，第二信号处理电路和接口多路复用器，其具有电连接到第一信号处理电路的第一输入端口，电连接到第二信号处理电路的第二输入端口和输出端 端口被布置成电连接到第一输入端口或第二输入端口。 电路板承载集成电路并且具有多个连接器放置位置，包括至少第一连接器放置位置，每个专用于第一信号处理电路和至少第二连接器放置位置，每个专用于第二信号处理电路。 接口多路复用器的连接器放置位置和输出端口串联电连接。 连接器安装在其中一个连接器放置位置上。

公开(公告)号：US20130088929A1

公开(公告)日：2013-04-11

申请号：US13617394

申请日：2012-09-14

申请人： Yan-Bin LUO ,  Chih-Chien HUNG ,  Qui-Ting CHEN ,  Shang-Ping CHEN

发明人： Yan-Bin LUO ,  Chih-Chien HUNG ,  Qui-Ting CHEN ,  Shang-Ping CHEN

IPC分类号： G11C7/10

CPC分类号： G06F13/16 ,  G06F1/3275 ,  G06F13/1668 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/06 ,  Y02D10/13 ,  Y02D10/14

摘要： A memory controller is provided. The memory controller is powered by first and second power source and includes an input/output pin, a driver circuit, a terminal resistor, and an input buffer. The driver circuit is coupled to the input/output pin and capable of providing to a writing signal to the input/output pin. The terminal resistor is coupled between the input/output pin and the first power source. The input buffer is coupled to the input/output pin and capable of receiving a reading signal from the input/output pin. No terminal resistor is coupled between the input/output pin and the second power source.

摘要翻译： 提供存储器控制器。 存储器控制器由第一和第二电源供电，并且包括输入/​​输出引脚，驱动器电路，终端电阻器和输入缓冲器。 驱动器电路耦合到输入/输出引脚，并且能够向输入/输出引脚提供写入信号。 端子电阻耦合在输入/输出引脚和第一个电源之间。 输入缓冲器耦合到输入/输出引脚，并能够从输入/输出引脚接收读取信号。 输入/输出引脚和第二个电源之间没有端子电阻耦合。

公开(公告)号：US08416005B2

公开(公告)日：2013-04-09

申请号：US12917894

申请日：2010-11-02

申请人： Yan-Bin Luo ,  Tun-Shih Chen ,  Min-Chung Chou

发明人： Yan-Bin Luo ,  Tun-Shih Chen ,  Min-Chung Chou

IPC分类号： H03L5/00

CPC分类号： H03K19/018528 ,  H04L25/0272 ,  H04L25/028

摘要： A multifunctional output driver capable of transmitting signals of different interfaces in different modes is provided, in which first and second current sources are provided, and first to fourth switching devices are coupled between the first and second current sources, and the first and second current source and the first to the fourth switching devices act as a current steering circuit. In a first transmission mode, the first and second switching devices are turned off, and the third and fourth switching devices and the first current source act as a current mode logic circuit to provide an output signal compatible with a first transmission interface according to an input signal from a pre-driver. In a second transmission mode, the current steering circuit outputs an output signal compatible with a second transmission interface according to the input signal from the pre-driver.

摘要翻译： 提供能够以不同模式发送不同接口的信号的多功能输出驱动器，其中提供第一和第二电流源，并且第一至第四开关器件耦合在第一和第二电流源之间，第一和第二电流源 并且第一至第四开关装置用作电流转向电路。 在第一传输模式中，第一和第二开关器件被关断，并且第三和第四开关器件和第一电流源用作电流模式逻辑电路，以根据输入提供与第一传输接口兼容的输出信号 来自前驱动器的信号。 在第二传输模式中，当前转向电路根据来自预驱动器的输入信号输出与第二传输接口兼容的输出信号。

公开(公告)号：US07990293B2

公开(公告)日：2011-08-02

申请号：US12499065

申请日：2009-07-07

申请人： Yan-Bin Luo

发明人： Yan-Bin Luo

IPC分类号： H03M9/00

CPC分类号： H03M9/00

摘要： A deserializer for converting serial data into at least one parallel data includes a first flip-flop group, a second flip-flop group and a programmable frequency divider. The first flip-flop group includes a plurality of flip-flops connected in series, where the first flip-flop group is controlled by a first clock signal. The second flip-flop group includes a plurality of flip-flops, where the second flip-flop group is controlled by a second clock signal, and the flip-flops of the second flip-flop group are respectively connected to output nodes of the flip-flops of the first flip-flop group. The programmable frequency divider is coupled to each of the flip-flops of the second flip-flop group, and is utilized for receiving a control signal and generating the second clock signal by performing a frequency-dividing operation according to a frequency-dividing factor set by the control signal.

摘要翻译： 用于将串行数据转换成至少一个并行数据的解串器包括第一触发器组，第二触发器组和可编程分频器。 第一触发器组包括串联连接的多个触发器，其中第一触发器组由第一时钟信号控制。 第二触发器组包括多个触发器，其中第二触发器组由第二时钟信号控制，并且第二触发器组的触发器分别连接到翻盖的输出节点 - 第一个触发器组的翻页。 可编程分频器耦合到第二触发器组的每个触发器，并且用于通过根据分频因子集执行分频操作来接收控制信号并产生第二时钟信号 通过控制信号。