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公开(公告)号：US11963356B2
公开(公告)日：2024-04-16
申请号：US17556745
申请日：2021-12-20
发明人： Zongliang Huo , Haohao Yang , Wei Xu , Ping Yan , Pan Huang , Wenbin Zhou
摘要： Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a stack structure including a memory block including a plurality of memory cells. The 3D memory device also includes a first top select structure and a bottom select structure in the memory block and aligned with each other vertically; and a second top select structure in the memory block is separated from the first top select structure by at least one of the plurality of memory cells. The first top select structure, the bottom select structure, and the second top select structure each includes an insulating material.
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2.发明公开公开(公告)号：US20230292511A1
公开(公告)日：2023-09-14
申请号：US18199333
申请日：2023-05-18
发明人： Zongliang Huo , Haohao Yang , Wei Xu , Ping Yan , Pan Huang , Wenbin Zhou
摘要： A three-dimensional (3D) memory device includes a memory stack including interleaved a plurality of conductor layers and a plurality of insulating layers extending laterally in the memory stack, a memory block including a plurality of channel structures extending vertically through the memory stack, a plurality of source structures extending vertically and laterally in the memory stack and being in contact with the memory block, and a plurality of conductor portions and a plurality of insulating portions being interleaved and locating between two adjacent source structures along a direction which the source structure extends. The interleaved plurality of conductor portions and plurality of insulating portions are each in contact with corresponding conductor layers and corresponding insulating layers of the same level from adjacent memory blocks.
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公开(公告)号：US20220115402A1
公开(公告)日：2022-04-14
申请号：US17556745
申请日：2021-12-20
发明人： Zongliang Huo , Haohao Yang , Wei Xu , Ping Yan , Pan Huang , Wenbin Zhou
IPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157
摘要： Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a stack structure including a memory block including a plurality of memory cells. The 3D memory device also includes a first top select structure and a bottom select structure in the memory block and aligned with each other vertically; and a second top select structure in the memory block is separated from the first top select structure by at least one of the plurality of memory cells. The first top select structure, the bottom select structure, and the second top select structure each includes an insulating material.
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公开(公告)号：US20220115395A1
公开(公告)日：2022-04-14
申请号：US17645102
申请日：2021-12-20
发明人： QIANG XU , Zhiliang Xia , Ping Yan , Guangji Li , Zongliang Huo
IPC分类号： H01L27/11578 , H01L27/11575 , H01L21/762 , H01L27/11582 , H01L27/11565 , H01L27/1157
摘要： The present disclosure describes method and structure of a three-dimensional memory device. The memory device includes a substrate and a plurality of wordlines extending along a first direction over the substrate. The first direction is along the x direction. The plurality of wordlines form a staircase structure in a first region. A plurality of channels are formed in a second region and through the plurality of wordlines. The second region abuts the first region at a region boundary. The memory device also includes an insulating slit formed in the first and second regions and along the first direction. A first width of the insulating slit in the first region measured in a second direction is greater than a second width of the insulating slit in the second region measured in the second direction.
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公开(公告)号：US11257831B2
公开(公告)日：2022-02-22
申请号：US16797030
申请日：2020-02-21
发明人： Wenxiang Xu , Haohao Yang , Pan Huang , Ping Yan , Zongliang Huo , Wenbin Zhou , Wei Xu
IPC分类号： H01L27/11519 , H01L27/11539 , H01L23/522 , H01L27/11556 , H01L27/11565 , H01L27/11582
摘要： Embodiments of three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a top selective gate cut and two structure strengthen plugs in an upper portion of the alternating dielectric stack, wherein each structure strengthen plug has a narrow support body and two enlarged connecting portions; forming a plurality of channel structures in the alternating dielectric stack; forming a plurality of gate line silts in the alternating dielectric stack, wherein each gate line slit exposes a sidewall of one enlarged connecting portion of a corresponding structure strengthen plug; transforming the alternating dielectric stack into an alternating conductive/dielectric stack; and forming a gate line slit structure in each gate line slit including an enlarged end portion connected to one enlarged connecting portion of a corresponding structure strengthen plug.
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公开(公告)号：US11251195B2
公开(公告)日：2022-02-15
申请号：US16670586
申请日：2019-10-31
发明人： Zongliang Huo , Haohao Yang , Wei Xu , Ping Yan , Pan Huang , Wenbin Zhou
IPC分类号： H01L27/11582 , H01L27/1157 , H01L27/11565
摘要： Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the 3D memory device includes a stack structure. The stack structure includes a plurality of conductor layers and a plurality of insulating layers interleaved over a substrate. The plurality of conductor layers include a pair of top select conductor layers divided by a first top select structure and a pair of bottom select conductor layers divided by a bottom select structure. The first top select structure and the bottom select structure extend along a horizontal direction and are aligned along a vertical direction. A plurality of channel structures extend along a vertical direction and into the substrate and are distributed on both sides of the top select structure and the bottom select structure.
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公开(公告)号：US20210167084A1
公开(公告)日：2021-06-03
申请号：US17148551
申请日：2021-01-13
发明人： Qingqing Wang , Wei Xu , Pan Huang , Ping Yan , Zongliang Huo , Wenbin Zhou
IPC分类号： H01L27/11582 , H01L23/528 , H01L27/1157 , H01L27/11565
摘要： A method for forming a three-dimensional (3D) memory device includes forming a cut structure in a stack structure. The stack structure includes interleaved a plurality of initial sacrificial layers and a plurality of initial insulating layers. The method also includes removing portions of the stack structure adjacent to the cut structure to form a slit structure and an initial support structure. The initial support structure divides the slit structure into a plurality of slit openings. The method further includes forming a plurality of conductor portions in the initial support structure through the plurality of slit openings. The method also includes forming a source contact in each of the plurality of slit openings. The method also includes removing portions of the initial support structure to form a support structure. The support structure includes an adhesion portion extending through the support structure. In addition, the method includes forming an adhesion layer over the source contact in each of the plurality of slit openings. At least two adhesion layers are conductively connected to the adhesion portion extending through the support structure.
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公开(公告)号：US20210104549A1
公开(公告)日：2021-04-08
申请号：US17100874
申请日：2020-11-21
发明人： Zongliang Huo , Haohao Yang , Wei Xu , Ping Yan , Pan Huang , Wenbin Zhou
IPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157
摘要： Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a method for forming a 3D memory device includes forming a bottom select structure extending along a vertical direction through a bottom conductor layer over a substrate and along a horizontal direction to divide the bottom conductor layer into a pair of bottom select conductor layers, forming a plurality of conductor layers and a plurality of insulating layers interleaved on the pair of bottom select conductor layers and the bottom select structure, and forming a plurality of channel structures extending along the vertical direction through the pair of bottom select conductor layers, the plurality of conductor layers, and the plurality of insulating layers and into the substrate. The method may further include forming a first top select structure extending along the vertical direction through a top conductor layer of the plurality of conductor layers and along the horizontal direction to divide the top conductor layer into a pair of top select conductor layers. The first top select structure and the bottom select structure may be aligned along the vertical direction and may divide a plurality of memory cells formed by the plurality of conductor layers and the plurality of channel structures into a pair of memory blocks.
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公开(公告)号：US20210066461A1
公开(公告)日：2021-03-04
申请号：US16689539
申请日：2019-11-20
发明人： Zhengliang Xia , Pan Huang , Wei Xu , Ping Yan , Zongliang Huo , Wenbin Zhou
IPC分类号： H01L29/417 , H01L27/11582 , H01L21/8234
摘要： A three-dimensional (3D) memory device includes a memory stack over a substrate. The memory stack includes interleaved a plurality of conductor layers and a plurality of insulating layers. The 3D memory device also includes a plurality of channel structures extending vertically in the memory stack. The 3D memory device further includes a source structure extending in the memory stack. The source structure includes a support structure dividing the source structure into first and second sections. The source structure also includes an adhesion layer. At least a portion of the adhesion layer extends through the support structure and conductively connects the first and second sections.
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公开(公告)号：US12035523B2
公开(公告)日：2024-07-09
申请号：US17532675
申请日：2021-11-22
发明人： Wenxiang Xu , Haohao Yang , Pan Huang , Ping Yan , Zongliang Huo , Wenbin Zhou , Wei Xu
摘要： Embodiments of three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a structure strengthen plug in an upper portion of the alternating dielectric stack, wherein the structure strengthen plug has a narrow support body and two enlarged connecting portions; forming a gate line silt in the alternating dielectric stack to expose a sidewall of one enlarged connecting portion of the structure strengthen plug; and forming a gate line slit structure in the gate line slit including an enlarged end portion connected to the one enlarged connecting portion of the structure strengthen plug.
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