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1.发明公开公开(公告)号：US20240362169A1
公开(公告)日：2024-10-31
申请号：US18472210
申请日：2023-09-21
IPC分类号： G06F12/1018 , G06F12/0873
CPC分类号： G06F12/1018 , G06F12/0873
摘要： An example memory controller and readable storage medium are disclosed. An example memory system includes: a non-volatile memory device and a memory controller coupled to the non-volatile memory device; the memory controller is configured to: determine whether data for the logical block address mapping of a received read command belongs to tables of a first class or tables of a second class, and confirm the heat of the data corresponding to the logical block address of the received read command; determine a level of the amount of drift of a threshold voltage of a memory cell corresponding to the logical block address, according to the heat of the data corresponding to the logical block address of the received read command; determine different read voltages that are correspondingly sent to the memory cell corresponding to the logical block address, according to different levels of the amount of drift.
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公开(公告)号：US12131924B2
公开(公告)日：2024-10-29
申请号：US17119665
申请日：2020-12-11
发明人： Liquan Cai , Peng Chen , Houde Zhou
CPC分类号： H01L21/67253 , B23K26/38 , H01L21/67092 , H01L21/67288
摘要： The present disclosure describes methods and systems for processing semiconductor wafers. A method for processing a wafer includes measuring one or more wafer characteristics of the wafer using a plurality of detectors. The wafer includes a device region and a perimeter region. The method also includes determining a wafer modification profile of the wafer based on the measured one or more wafer characteristics. The method further includes modifying a ring-shaped portion of the wafer within the perimeter region using the wafer modification profile. The modified ring-shaped portion has a penetration depth that is less than a thickness of the wafer. The method further includes performing a wafer thinning process on the wafer.
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公开(公告)号：US20240355694A1
公开(公告)日：2024-10-24
申请号：US18366112
申请日：2023-08-07
发明人： Huayang YU , Qingyi HUANG , Pengzhen ZHANG , Zhen PAN , Xijin PENG , Shuai HU , Mengting WANG , Qikang HUANG
IPC分类号： H01L23/31 , H01L21/56 , H10B41/20 , H10B41/35 , H10B41/40 , H10B43/20 , H10B43/35 , H10B43/40
CPC分类号： H01L23/3157 , H01L21/56 , H10B41/20 , H10B41/35 , H10B41/40 , H10B43/20 , H10B43/35 , H10B43/40
摘要： The present disclosure discloses a memory, a fabrication method thereof, and a memory system. According to an example, the memory includes a substrate, a device layer, a padding layer and a buffering protection layer. The device layer is disposed on the substrate, the padding layer is disposed at a first side of the device layer, the buffering protection layer is disposed on a second side of the device layer and a side of the padding layer away from the substrate. The padding layer is disposed to be adjacent to the device layer in a direction parallel to the substrate.
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公开(公告)号：US12125827B2
公开(公告)日：2024-10-22
申请号：US18195096
申请日：2023-05-09
发明人： XinRu Zeng , Peng Chen , Houde Zhou
IPC分类号： H01L25/065 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/538 , H01L25/00
CPC分类号： H01L25/0657 , H01L21/56 , H01L23/3121 , H01L23/3135 , H01L23/5384 , H01L24/05 , H01L25/50
摘要： A chip package structure includes multiple chips stacked together, a molding layer encapsulating the multiple chips, a conductive layer is on a side of the molding layer away from the multiple chips, and a vertical conductive element extending from a surface of the molding layer to the bonding pad. Each of the multiple chips includes a bonding pad not covered by the multiple chips. The vertical conductive element connects the conductive layer and the bonding pad. The vertical conductive element includes gold.
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公开(公告)号：US12118228B2
公开(公告)日：2024-10-15
申请号：US17687004
申请日：2022-03-04
发明人： Yonggang Chen
IPC分类号： G06F3/06
CPC分类号： G06F3/0653 , G06F3/0604 , G06F3/0689
摘要： The present disclosure provides a system. The system includes a memory device and a controller. The memory device is configured to store memory data and includes a plurality of memory modules. Each of the memory modules includes a first memory block and a second memory block. The controller includes a processor and a memory. The controller is operatively coupled to the plurality of memory modules. In an operation on redundant array of independent disks (RAID), the controller is configured to generate a first check code based on memory data in the first memory block of the plurality memory modules, generate a second check code based on memory data in the second memory block of the plurality memory modules, and generate an additional check code based on the first check code and the second check code.
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公开(公告)号：US20240341096A1
公开(公告)日：2024-10-10
申请号：US18746944
申请日：2024-06-18
发明人： Kun Zhang , Zhong Zhang , Lei Liu , Wenxi Zhou , Zhiliang Xia
IPC分类号： H10B43/27 , H01L23/528 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/35 , H10B43/40
CPC分类号： H10B43/27 , H01L23/5283 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/35 , H10B43/40
摘要： A three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers over a first side of a second semiconductor layer, channel structures extending vertically through the memory stack and into the second semiconductor layer, source contacts in contact with a second side of the second semiconductor layer opposite to the first side; and a backside interconnect layer over the second side of the second semiconductor layer and including interlayer dielectric (ILD) layers and a source line mesh on the ILD layers. The source contacts are distributed on a side of the source line mesh. The source contacts extend through the ILD layers and into the second semiconductor layer.
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公开(公告)号：US20240334690A1
公开(公告)日：2024-10-03
申请号：US18676298
申请日：2024-05-28
发明人： Kun Zhang , Wenxi Zhou
摘要： Memory devices and methods for forming the same are disclosed. In certain aspects, a memory device includes a filling layer; a stack structure including interleaved conductive layers and dielectric layers; a channel structure extending through the stack structure and the filling layer. The channel structure includes a memory film and a semiconductor channel. The memory device also includes a doped semiconductor layer in contact with the semiconductor channel. The filling layer is between the doped semiconductor layer and the stack structure. The memory device further includes an insulating layer, and a source contact extending through the insulating layer and in contact with the doped semiconductor layer. The doped semiconductor layer is between the insulating layer and the filling layer.
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公开(公告)号：US20240332152A1
公开(公告)日：2024-10-03
申请号：US18227266
申请日：2023-07-27
发明人： Xinru Zeng , Peng Chen
IPC分类号： H01L23/498 , H01L21/56 , H01L23/00 , H01L23/31 , H01L25/065
CPC分类号： H01L23/49827 , H01L21/568 , H01L23/3128 , H01L24/05 , H01L24/32 , H01L25/0652 , H01L25/0657 , H01L2224/08155 , H01L2224/32146 , H01L2224/32235 , H01L2225/06541 , H01L2225/1047 , H01L2924/1436 , H01L2924/15311 , H01L2924/1811
摘要： The present application provides an integrated package device, a method of fabricating an integrated package device, and a memory system. The integrated package device may include at least one package module. Each package module may include a first sub-package module with a first electronic devices. Each package module may include a second sub-package module including a second electronic devices. Each package module may include a first re-distribution layer connected with first pads. Each package module may include a second re-distribution layer connected with second pads.
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9.发明授权公开(公告)号：US12106985B2
公开(公告)日：2024-10-01
申请号：US17307944
申请日：2021-05-04
发明人： Liquan Cai , Peng Chen , Houde Zhou
IPC分类号： H01L21/67 , B23K26/364 , H01L21/268 , H01L21/66 , H01L21/78 , H01L23/544
CPC分类号： H01L21/67282 , B23K26/364 , H01L21/268 , H01L21/67092 , H01L21/67115 , H01L21/78 , H01L22/20 , H01L23/544 , H01L2223/5442
摘要： A laser dicing system is disclosed. The laser dicing system includes a host device and a laser source. The host device reads and identifies a mark formed on a surface of a semiconductor structure. The laser source is coupled to the host device and is configured to generate a dicing laser energy to form a trench on the semiconductor structure. The dicing laser energy irradiated on the semiconductor structure is adjustable based on information embedded in the mark.
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公开(公告)号：US12106810B2
公开(公告)日：2024-10-01
申请号：US18217987
申请日：2023-07-03
发明人： Jialiang Deng , Zhuqin Duan , Lei Shi , Yuesong Pan , Yanlan Liu , Bo Li
CPC分类号： G11C16/26 , G11C16/08 , G11C16/102 , G11C16/14 , H03K19/1737
摘要： A memory device includes N memory planes (N is an integer greater than 1), M asynchronous multi-plane independent (AMPI) read units (M is an integer smaller than or equal to N), a first microcontroller unit (MCU), and a multiplexing circuit coupled to the N memory planes, the first MCU, and the M AMPI read units. Each AMPI read unit is configured to provide an AMPI read control signal for a respective memory plane to control an AMPI read operation on the respective memory plane. The first MCU is configured to provide a non-AMPI read control signal for each memory plane to control a non-AMPI read operation on each memory plane. The multiplexing circuit is configured to, in a non-AMPI read operation, direct a non-AMPI read control signal to each memory plane from the first MCU, and in an AMPI read operation, direct each AMPI read control signal of M AMPI read control signals to the respective memory plane from the corresponding AMPI read unit.
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