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公开(公告)号：US11716850B2
公开(公告)日：2023-08-01
申请号：US17170872
申请日：2021-02-08
发明人： Zongliang Huo , Haohao Yang , Wei Xu , Ping Yan , Pan Huang , Wenbin Zhou
IPC分类号： H01L27/11582 , H10B43/27 , H10B43/10 , H10B43/35
摘要： A method for forming a 3D memory device is provided. The method includes forming a dielectric stack including interleaved initial insulating layers and initial sacrificial layers over a substrate, and forming at least one slit structure extending vertically and laterally in the dielectric stack and dividing the dielectric stack into block regions. The at least one slit structure each includes slit openings exposing the substrate and an initial support structure between adjacent slit openings. Each block region may include interleaved insulating layers and sacrificial layers, and the initial support structure may include interleaved insulating portions and sacrificial portions. Each insulating portion and sacrificial portion may be in contact with respective insulating layers and sacrificial layers of a same level from adjacent block regions. The method also includes forming channel structures extending vertically through the dielectric stack, replacing the sacrificial layers and sacrificial portions with conductor layers and conductor portions through the at least one slit structure, and forming a source structure in each slit structure. The source structure may include an insulating spacer in each slit opening and a source contact in a respective insulating spacer.
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公开(公告)号：US11145667B2
公开(公告)日：2021-10-12
申请号：US16367299
申请日：2019-03-28
发明人： Ruo Fang Zhang , Enbo Wang , Haohao Yang , Qianbing Xu , Yushi Hu , Fushan Zhang
IPC分类号： H01L27/11524 , H01L27/11556 , G11C5/06 , H01L27/1157 , H01L27/11582
摘要： In a memory device, a lower memory cell string is formed over a substrate to include a first channel structure, a plurality of first word line layers and first insulating layers. The first channel structure protrudes from the substrate and passes through the first word line layers and first insulating layers. An inter deck contact is formed over the lower memory cell string and connected with the first channel structure. An upper memory cell string is formed over the inter deck contact. The upper memory cell string includes a second channel structure, a plurality of second word lines and second insulating layers. The second channel structure passes through the second word lines and second insulating layers, and extends to the inter deck contact, and further extends laterally into the second insulating layers. A channel dielectric region of the second channel structure is above the inter deck contact.
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公开(公告)号：US20210167086A1
公开(公告)日：2021-06-03
申请号：US17170872
申请日：2021-02-08
发明人： Zongliang Huo , Haohao Yang , Wei Xu , Ping Yan , Pan Huang , Wenbin Zhou
IPC分类号： H01L27/11582 , H01L27/11565
摘要： A method for forming a 3D memory device is provided. The method includes forming a dielectric stack including interleaved initial insulating layers and initial sacrificial layers over a substrate, and forming at least one slit structure extending vertically and laterally in the dielectric stack and dividing the dielectric stack into block regions. The at least one slit structure each includes slit openings exposing the substrate and an initial support structure between adjacent slit openings. Each block region may include interleaved insulating layers and sacrificial layers, and the initial support structure may include interleaved insulating portions and sacrificial portions. Each insulating portion and sacrificial portion may be in contact with respective insulating layers and sacrificial layers of a same level from adjacent block regions. The method also includes forming channel structures extending vertically through the dielectric stack, replacing the sacrificial layers and sacrificial portions with conductor layers and conductor portions through the at least one slit structure, and forming a source structure in each slit structure. The source structure may include an insulating spacer in each slit opening and a source contact in a respective insulating spacer.
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公开(公告)号：US20200111807A1
公开(公告)日：2020-04-09
申请号：US16194267
申请日：2018-11-16
发明人： Qianbin Xu , Haohao Yang , EnBo Wang , Yong Zhang , Jialan He
IPC分类号： H01L27/11582 , H01L27/1157
摘要： Embodiments of 3D memory devices having an inter-deck plug and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a first memory deck including interleaved conductor and dielectric layers above the substrate, a second memory deck including interleaved conductor and dielectric layers above the first memory deck, and a first and a second channel structure each extending vertically through the first or second memory deck. The first channel structure includes a first memory film and semiconductor channel along a sidewall of the first channel structure, and an inter-deck plug in an upper portion of the first channel structure and in contact with the first semiconductor channel. A lateral surface of the inter-deck plug is smooth. The second channel structure includes a second memory film and semiconductor channel along a sidewall of the second channel structure. The second semiconductor channel is in contact with the inter-deck plug.
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5.发明申请公开(公告)号：US20200105781A1
公开(公告)日：2020-04-02
申请号：US16194273
申请日：2018-11-16
发明人： Haohao Yang , Yong Zhang , EnBo Wang , Ruo Fang Zhang , Fushan Zhang , Qianbin Xu
IPC分类号： H01L27/11578 , H01L27/06 , H01L27/10 , H01L27/11565 , H01L27/11551 , G11C16/04
摘要： Embodiments of 3D memory devices with a semiconductor plug protected by a dielectric layer and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including a plurality of interleaved conductor layers and dielectric layers on the substrate, and a memory string extending vertically through the memory stack. The memory string includes a semiconductor plug in a lower portion of the memory string, a protective dielectric layer on the semiconductor plug, and a memory film above the protective dielectric layer and along a sidewall of the memory string.
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公开(公告)号：US11765897B2
公开(公告)日：2023-09-19
申请号：US17100874
申请日：2020-11-21
发明人： Zongliang Huo , Haohao Yang , Wei Xu , Ping Yan , Pan Huang , Wenbin Zhou
摘要： Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a method for forming a 3D memory device includes forming a bottom select structure extending along a vertical direction through a bottom conductor layer over a substrate and along a horizontal direction to divide the bottom conductor layer into a pair of bottom select conductor layers, forming a plurality of conductor layers and a plurality of insulating layers interleaved on the pair of bottom select conductor layers and the bottom select structure, and forming a plurality of channel structures extending along the vertical direction through the pair of bottom select conductor layers, the plurality of conductor layers, and the plurality of insulating layers and into the substrate. The method may further include forming a first top select structure extending along the vertical direction through a top conductor layer of the plurality of conductor layers and along the horizontal direction to divide the top conductor layer into a pair of top select conductor layers. The first top select structure and the bottom select structure may be aligned along the vertical direction and may divide a plurality of memory cells formed by the plurality of conductor layers and the plurality of channel structures into a pair of memory blocks.
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公开(公告)号：US11737263B2
公开(公告)日：2023-08-22
申请号：US17446006
申请日：2021-08-26
发明人： Ruo Fang Zhang , Enbo Wang , Haohao Yang , Qianbing Xu , Yushi Hu , Fushan Zhang
摘要： In a three-dimensional memory device, an interconnect structure is formed over a substrate and a first deck is formed over the interconnect structure. The first deck includes alternating first insulating layers and first word line layers, and a first channel structure extending through the first stack. The first channel structure has a first channel dielectric region and a first channel layer. The first channel dielectric region is formed along sidewalls of the first channel structure, positioned over a top surface of the interconnect structure, and in contact with the first insulating layers and the first word line layers. The first channel layer is formed along the first channel dielectric region, and includes a rounded projection that extends away from the top surface of the interconnect structure, extends outwards into the first stack at an interface of the interconnect structure, the first channel structure and the first stack.
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公开(公告)号：US20230084008A1
公开(公告)日：2023-03-16
申请号：US17447456
申请日：2021-09-13
发明人： Zhenyu Lu , Jun Chen , Xiaowang Dai , Jifeng Zhu , Qian Tao , Yu Ru Huang , Si Ping Hu , Lan Yao , Li Hong Xiao , A Man Zheng , Kun Bao , Haohao Yang
IPC分类号： H01L23/535 , H01L23/528 , H01L23/532 , H01L21/768
摘要： A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.
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公开(公告)号：US20230083030A1
公开(公告)日：2023-03-16
申请号：US18054468
申请日：2022-11-10
发明人： Zhenyu Lu , Jun Chen , Xiaowang Dai , Jifeng Zhu , Qian Tao , Yu Ru Huang , Si Ping Hu , Lan Yao , Li Hong Xiao , A Man Zheng , Kun Bao , Haohao Yang
IPC分类号： H01L23/535 , H01L21/768 , H01L23/528 , H01L23/532
摘要： A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.
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公开(公告)号：US20210398999A1
公开(公告)日：2021-12-23
申请号：US17462736
申请日：2021-08-31
发明人： Ruo Fang ZHANG , Enbo Wang , Haohao Yang , Qianbing Xu , Yushi Hu , Qian Tao
IPC分类号： H01L27/11556 , H01L27/11524
摘要： Aspects of the disclosure provide methods for manufacturing semiconductor devices. One of the methods forms a string of transistors in a semiconductor device over a substrate of the semiconductor device. The method includes forming a first substring of transistors having a first channel structure that includes a first channel layer and a first gate dielectric structure that extend along a vertical direction over the substrate. The method includes forming a channel connector over the first substring and forming the second substring above the channel connector. The second substring has a second channel structure. The second channel structure includes the second channel layer and a second gate dielectric structure that extend along the vertical direction. The second gate dielectric structure is formed above the channel connector. The channel connector electrically couples the first channel layer and the second channel layer.
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