公开(公告)号：US06509609B1

公开(公告)日：2003-01-21

申请号：US09884345

申请日：2001-06-18

申请人： Yaohui Zhang ,  Bich-Yen Nguyen ,  Kuntal Joardar ,  Daniel Thanh-Khac Pham

发明人： Yaohui Zhang ,  Bich-Yen Nguyen ,  Kuntal Joardar ,  Daniel Thanh-Khac Pham

IPC分类号： H01L2978

CPC分类号： H01L29/66643 ,  H01L21/823437 ,  H01L21/823828 ,  H01L29/6656 ,  H01L29/66621 ,  H01L29/7834 ,  H01L29/7839

摘要： A grooved channel Schottky contacted MOSFET has asymmetric source and drain regions. The MOSFET includes an undoped silicon substrate with a background doping concentration of less than about 1017 cm−3. A grooved channel is formed in a first surface of the substrate. A first metal silicide material is formed in a first side of the grooved channel, forming a source region, and a second metal silicide material is formed on a second side of the grooved channel, forming a drain region. A metal gate is formed in the grooved channel. The grooved structure allows the off-state current to be reduced to less than 50 pA/&mgr;m. Further, the feature size can be scaled down to 10 nm without strong short-channel effects (DIBL

摘要翻译： 沟槽沟道肖特基接触MOSFET具有不对称的源极和漏极区域。 MOSFET包括背景掺杂浓度小于约1017cm-3的未掺杂硅衬底。 在基板的第一表面中形成开槽通道。 第一金属硅化物材料形成在带槽沟道的第一侧，形成源极区，并且第二金属硅化物材料形成在带槽沟道的第二侧上，形成漏区。 在沟槽通道中形成金属门。 带槽结构允许关断状态电流降低到小于50pA / mum。 此外，特征尺寸可以缩小到10nm，而没有强的短信道效应（DIBL <0.063），并且门延迟（CV / I）降低到2.4ps。

公开(公告)号：US5900763A

公开(公告)日：1999-05-04

申请号：US317673

申请日：1994-10-11

申请人： Irfan Rahim ,  Bor-Yuan Hwang ,  Kuntal Joardar

发明人： Irfan Rahim ,  Bor-Yuan Hwang ,  Kuntal Joardar

IPC分类号： H01L21/761 ,  H01L27/02 ,  H01L27/088 ,  H01L21/26

CPC分类号： H01L27/088 ,  H01L21/761 ,  H01L27/0203

摘要： An integrated circuit (10) provides analog and digital circuitry on a common substrate (12). A first digital circuit (14) operates in combination with an analog circuit (18) to perform a useful function. A second duplicate digital circuit (26) is disposed adjacent to the first digital circuit and operates out-of-phase with respect to the first digital circuit. The second duplicate digital circuit introduces voltage spikes equal and opposite to the voltage spikes introduced into the substrate by the first digital circuit. The equal and opposite voltage spikes tend to cancel and thereby minimize cross-talk between the digital and analog circuits. A guard ring (16,28) surrounds each of the first and second digital circuits and the analog circuit to reduce voltage spikes into the substrates. By minimizing cross-talk, the analog circuit operates without interference from the digital circuits.

摘要翻译： 集成电路（10）在公共基板（12）上提供模拟和数字电路。 第一数字电路（14）与模拟电路（18）组合工作以执行有用的功能。 第二重复数字电路（26）被布置为与第一数字电路相邻并且相对于第一数字电路进行异相操作。 第二重复数字电路引入与由第一数字电路引入衬底的电压尖峰相等和相反的电压尖峰。 相等和相反的电压尖峰趋于抵消，从而最小化数字和模拟电路之间的串扰。 保护环（16,28）围绕第一和第二数字电路和模拟电路中的每一个以减少到基板的电压尖峰。 通过最小化串扰，模拟电路在数字电路没有干扰的情况下工作。

公开(公告)号：US06225674B1

公开(公告)日：2001-05-01

申请号：US09285532

申请日：1999-04-02

申请人： Ik-Sung Lim ,  David G. Morgan ,  Kuntal Joardar

发明人： Ik-Sung Lim ,  David G. Morgan ,  Kuntal Joardar

IPC分类号： H01L2900

CPC分类号： H01L29/1087 ,  H01L21/761 ,  H01L21/76205 ,  H01L21/763 ,  H01L21/765 ,  H01L23/552 ,  H01L29/10 ,  H01L29/1083 ,  H01L29/41 ,  H01L29/7317 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure (10) having device isolation structures (43, 44) and shielding structures (39, 40). The shielding structures (39, 40) are formed in a semiconductor material (11) and the device isolation structures (43, 44) are formed within the corresponding shielding structures (39, 40). A noise generating device is formed within a first shielding structure (43) and a noise sensitive device is formed within a second shielding structure (44). The two shielding structures (39, 40) are grounded and prevent noise from the noise generating device from interfering with the noise sensitive device.

摘要翻译： 具有器件隔离结构（43,44）和屏蔽结构（39,40）的半导体结构（10）。 屏蔽结构（39,40）形成在半导体材料（11）中，并且器件隔离结构（43,44）形成在相应的屏蔽结构（39,40）内。 噪声产生装置形成在第一屏蔽结构（43）内，噪声敏感装置形成在第二屏蔽结构（44）内。 两个屏蔽结构（39,40）接地，防止来自噪声产生装置的噪声干扰噪声敏感装置。

公开(公告)号：US5936454A

公开(公告)日：1999-08-10

申请号：US69803

申请日：1993-06-01

申请人： Kuntal Joardar

发明人： Kuntal Joardar

IPC分类号： H01L27/07 ,  H03K17/567 ,  H03K17/60

CPC分类号： H01L27/0722 ,  H03K17/567

摘要： A laterally formed bipolar transistor receives independent base biasing at a base terminal and gate biasing at a gate terminal for providing high forward current gain and improved frequency response. The collector and emitter are formed with a first conductivity type and disposed in a well having a second conductivity type. The gate of the lateral transistor is formed adjacent to the well between the collector and emitter and receives the gate bias. The base of the lateral transistor is formed adjacent to the well and receiving the base bias. The combination of independent base and gate biasing provides more mobile carries to improve the forward current gain and frequency response of the lateral transistor while reducing its overall area.

摘要翻译： 横向形成的双极晶体管在基极端子处接收独立的基极偏置，并在栅极端子处施加栅偏置，以提供高正向电流增益和改进的频率响应。 集电极和发射极形成为具有第一导电类型并且设置在具有第二导电类型的阱中。 横向晶体管的栅极与集电极和发射极之间的阱相邻形成，并接收栅极偏置。 横向晶体管的基极形成为与阱接近并接收基极偏压。 独立基极和栅极偏置的组合提供更多的移动载体，以改善横向晶体管的正向电流增益和频率响应，同时减小其整体面积。

公开(公告)号：US5623159A

公开(公告)日：1997-04-22

申请号：US625685

申请日：1996-04-04

申请人： David J. Monk ,  Kuntal Joardar

发明人： David J. Monk ,  Kuntal Joardar

IPC分类号： H01L21/761 ,  H01L27/06 ,  H01L27/04

CPC分类号： H01L27/0623 ,  H01L21/761 ,  Y10S257/929

摘要： An improved isolation structure for a semiconductor device includes a p-type semiconductor substrate (12) with a p-type well (28) disposed in the substrate (12). A continuous plurality of n-type regions (14, 16, 26) is disposed around the p-type well (28), and the continuous plurality of n-type regions (14, 16, 26) fully isolates the p-type well (28) from the substrate (12) except that the continuous plurality of regions (14, 16, 26) comprises one or more p-type gaps (18) that electrically connect the p-type well (28) to the p-type substrate (12). The use of the gap (18) improves cross-talk suppression in mixed-mode integrated circuits at higher frequencies, for example greater than 50 MHz.

摘要翻译： 用于半导体器件的改进的隔离结构包括具有设置在衬底（12）中的p型阱（28）的p型半导体衬底（12）。 连续多个n型区域（14,16,26）围绕p型阱（28）设置，并且连续的多个n型区域（14,16,26）将p型阱完全隔离 （28）与P型阱（28）电连接的一个或多个p型间隙（18），所述连续多个区域（14,16,26） 衬底（12）。 间隙（18）的使用改善了混频模式集成电路中在较高频率（例如大于50MHz）下的串扰抑制。

公开(公告)号：US5687355A

公开(公告)日：1997-11-11

申请号：US517046

申请日：1995-08-21

申请人： Kuntal Joardar ,  Kiran Kumar Gullapalli

发明人： Kuntal Joardar ,  Kiran Kumar Gullapalli

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5036

摘要： The present invention generates a model of a graded channel transistor having at least two channel portions of differing doping concentrations. The present invention assumes a uniform doping concentration of each channel portion. Each of the channel portions is modeled using a standard transistor model (100, 120) with junction voltages (64) resulting between the transistor models. The junction voltages (64) are determined to be at a level such that the channel currents of the transistor models (60, 62) are equal. Once the junction voltages (64) are determined, the parameters of the transistor models (60, 62) are determined. Once the transistor models (60, 62) are determined, the models are combined to produce a composite transistor model (70) for the transistor using standard circuit reduction techniques. The composite model produced is scalable with respect to geometry, is continuous, and is differentiable. Steps are also disclosed for manufacturing integrated circuits using the modeling techniques of the present invention.

摘要翻译： 本发明产生具有不同掺杂浓度的至少两个沟道部分的渐变沟道晶体管的模型。 本发明假设每个通道部分的掺杂浓度均匀。 使用具有在晶体管模型之间产生的结电压（64）的标准晶体管模型（100,120）来对每个沟道部分进行建模。 结电压（64）被确定为使得晶体管型号（60,62）的沟道电流相等的电平。 一旦确定了结电压（64），就确定晶体管模型（60,62）的参数。 一旦确定了晶体管模型（60,62），就使用标准电路还原技术将模型组合以产生用于晶体管的复合晶体管模型（70）。 生成的复合模型相对于几何是可扩展的，是连续的，并且是可微分的。 还公开了使用本发明的建模技术制造集成电路的步骤。

公开(公告)号：US5475255A

公开(公告)日：1995-12-12

申请号：US268744

申请日：1994-06-30

申请人： Kuntal Joardar ,  Jeffrey D. Ganger ,  Sangil Park

发明人： Kuntal Joardar ,  Jeffrey D. Ganger ,  Sangil Park

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L29/41

CPC分类号： H01L23/585 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S257/901

摘要： A circuit die 100 with improved substrate noise isolation may be achieved by providing a first circuit element 102 and a second circuit element 103 on a substrate 101. The first circuit element 102 generally injects noise into the substrate 101 while the second circuit element 103 is adversely affected by noise being carried in the substrate 101. To reduce the noise interference, a noise isolation ring 104-017 may be placed around the first circuit element 102 and/or the second circuit element 103 wherein the noise isolation ring is of a conducted material. A first lead 202 is electrically connected to a first circuit element 102, a second lead 205 is electrically connected to the second circuit element 103, and a third lead 201 is electrically connected to the noise isolation ring 105, wherein the third lead 201 is electrically isolated from both the first and second leads 202 and 205.

摘要翻译： 具有改善的衬底噪声隔离的电路管芯100可以通过在衬底101上设置第一电路元件102和第二电路元件103来实现。第一电路元件102通常将噪声注入到衬底101中，而第二电路元件103是不利的 受到在衬底101中承载的噪声的影响。为了减少噪声干扰，噪声隔离环104-017可以放置在第一电路元件102和/或第二电路元件103周围，其中噪声隔离环是导电材料 。 第一引线202电连接到第一电路元件102，第二引线205电连接到第二电路元件103，并且第三引线201电连接到噪声隔离环105，其中第三引线201是电 从第一引线202和第二引线205分离。

公开(公告)号：US5467057A

公开(公告)日：1995-11-14

申请号：US320427

申请日：1994-10-11

申请人： Kuntal Joardar

发明人： Kuntal Joardar

IPC分类号： H01L27/07 ,  H03F3/72 ,  H03G1/00 ,  H03G3/10 ,  H03F3/45 ,  H03G3/30

CPC分类号： H03G3/10 ,  H01L27/0722 ,  H03F3/72 ,  H03G1/0082

摘要： A variable gain amplifier (10) provides a controllable amplification of an input signal as determined by a gate voltage. The variable gain amplifier takes on the form of a differential amplifier with first and second emitter-coupled lateral NPN bipolar transistors (12, 26) each having a gate (60) spanning the base region (48). The bases of the first and second transistors are biased with resistors (20-22, 30-32) coupled between V.sub.cc and ground potential. The gate voltage effects the conductivity through the base region and provides control over the forward current gain of the transistors. A third lateral NPN bipolar transistor (70) is added in parallel with the first transistor and operates with a separate gate voltage to provide two modes of amplification.

摘要翻译： 可变增益放大器（10）提供由栅极电压确定的输入信号的可控放大。 可变增益放大器采用具有第一和第二发射极耦合横向NPN双极晶体管（12,26）的差分放大器的形式，每个具有跨过基极区域（48）的栅极（60）。 第一晶体管和第二晶体管的基极由耦合在Vcc和地电位之间的电阻器（20-22,30-32）偏置。 栅极电压通过基极区域影响电导率，并提供对晶体管正向电流增益的控制。 第三横向NPN双极晶体管（70）与第一晶体管并联并且以单独的栅极电压工作以提供两种放大模式。