公开(公告)号：US5946039A

公开(公告)日：1999-08-31

申请号：US911901

申请日：1997-08-15

申请人： Yaron Ben-Arie ,  Effi Orian ,  Itzhak Barak ,  Jacob Kirschenbaum ,  Yehuda Shvager ,  Shao-Wei Pan

发明人： Yaron Ben-Arie ,  Effi Orian ,  Itzhak Barak ,  Jacob Kirschenbaum ,  Yehuda Shvager ,  Shao-Wei Pan

IPC分类号： G06T9/00 ,  H04N7/26 ,  H04N7/30

CPC分类号： H04N19/126 ,  H04N19/60 ,  H04N19/124

摘要： An encoding system (400) receives samples and coefficients from a bus (422). The system comprises a plurality of parallel operating memory devices (430-k), registers (435-k), computing units (440-k), and accumulator units (460-k). The system (400) further comprises a parallel-to-serial buffer (470) coupled to the accumulator units (440-k) and a pair generator (480) for providing amplitude/index pairs. The system (400) performs encoding steps such as transforming, quantizing, zigzagging, rate controlling, and run-length coding. Transforming is explained for the example of a Forward Discrete Cosine Transformation (FDCT). According to a method (500) of the present invention, zigzagging (510) occurs prior to transforming (570) and performed only once when transformation coefficients are provided to the memory devices (430-k) in a zigzag arrangement. Quantizing occurs prior to transforming by pre-calculating the coefficients with quantizers. Pair generator (480) performes rate-controlling and run-length encoding (550). (with reference to FIGS. 2 and 9)

摘要翻译： 编码系统（400）从总线（422）接收采样和系数。 该系统包括多个并行操作存储器件（430-k），寄存器（435-k），计算单元（440-k）和累加器单元（460-k）。 系统（400）还包括耦合到累加器单元（440-k）的并行 - 串行缓冲器（470）和用于提供振幅/折射率对的一对发生器（480）。 系统（400）执行变换，量化，曲折，速率控制和游程长度编码等编码步骤。 对于前向离散余弦变换（FDCT）的示例解释变换。 根据本发明的方法（500），在变换之前发生锯齿形（510）（570），并且在以Z字形排列向存储器件（430-k）提供变换系数时仅执行一次。 通过用量化器预先计算系数，在变换前进行量化。 配对发生器（480）执行速率控制和游程长度编码（550）。 （参照图2和图9）

公开(公告)号：US5892755A

公开(公告)日：1999-04-06

申请号：US768013

申请日：1996-12-13

申请人： Yaron Ben-Arie ,  Roni Eliyahu ,  Ronen Shtayer ,  Yehuda Shvager

发明人： Yaron Ben-Arie ,  Roni Eliyahu ,  Ronen Shtayer ,  Yehuda Shvager

IPC分类号： H04Q3/00 ,  H04L12/56 ,  H04Q11/04

CPC分类号： H04L49/3081 ,  H04L49/30 ,  H04Q11/0478 ,  H04L2012/5679 ,  H04L2012/5681

摘要： A transfer layer of an ATM type used between a switch (216) and a number N of communication channels (218). Each communication channel (218) has second storage arrangement B.sub.0, . . . , B.sub.N-1 for storing cell queues having a length of up to P cells each, one of the second storage arrangements being in a busy condition if a minimum number M of cells is stored therein, where M is lesser of equal P. Each communication channel is assigned to one of the switch queues. The transfer layer (217) has third storage arrangement T for storage of a cell queue having a length of up to L cells. Furthermore the transfer layer (217) selectively disables the input of a cell from one of the switch queues into the third storage arrangement if the second storage arrangement is in a busy condition.

摘要翻译： 在交换机（216）和数目为N个通信信道（218）之间使用的ATM类型的传送层。 每个通信信道（218）具有第二存储布置B0，。 。 。 ，BN-1，用于存储每个具有多达P个单元的长度的单元队列，如果存储有最小数量M的单元，则第二存储装置中的一个处于忙状态，其中M较小的相等P。每个通信 通道分配给其中一个交换机队列。 转移层（217）具有第三存储装置T，用于存储具有长达L个小区的长度的小区队列。 此外，如果第二存储装置处于忙状态，则转移层（217）有选择地将小区的输入从交换队列之一进入第三存储装置。

公开(公告)号：US5485456A

公开(公告)日：1996-01-16

申请号：US326972

申请日：1994-10-21

申请人： Ronen Shtayer ,  Roni Eliyahu ,  Yehuda Shvager ,  Yaron Ben-Arie

发明人： Ronen Shtayer ,  Roni Eliyahu ,  Yehuda Shvager ,  Yaron Ben-Arie

IPC分类号： H04J3/24 ,  H04L12/56 ,  H04Q11/04

CPC分类号： H04J3/247 ,  H04Q11/0478 ,  H04L2012/5616 ,  H04L2012/5672

摘要： An asynchronous transfer mode (ATM) system has a plurality of physical layers (24, 50, 52, and 26) coupled to one ATM layer (12) for communicating ATM data cells. In order to allow bi-directional communication, both the receive interface and the transmit interface of FIGS. 14 and 15 are coupled between the ATM layer and each physical (PHY) layer in the plurality of physical layers. In order to identify which physical layer of the plurality of physical layers is to either receive or transmit a data cell, a physical layer ID byte is transmitted along with the UTOPIA protocol multi-byte ATM data cell to address one physical layer in the plurality of physical layers.

摘要翻译： 异步传输模式（ATM）系统具有耦合到一个ATM层（12）的多个物理层（24,50,52和26），用于传送ATM数据单元。 为了允许双向通信，图1和图2的接收接口和发送接口都是可以的。 14和15耦合在多个物理层中的ATM层和每个物理（PHY）层之间。 为了识别多个物理层的哪个物理层要接收或发送数据单元，物理层ID字节与UTOPIA协议多字节ATM数据单元一起发送以寻址多个物理层中的一个物理层 物理层。

公开(公告)号：US08572296B2

公开(公告)日：2013-10-29

申请号：US11994270

申请日：2005-06-30

申请人： Uri Shasha ,  Sagi Gurfinkel ,  Gilad Hassid ,  Eran Kahn ,  Yehuda Shvager

发明人： Uri Shasha ,  Sagi Gurfinkel ,  Gilad Hassid ,  Eran Kahn ,  Yehuda Shvager

IPC分类号： G06F13/28 ,  G06F13/36

CPC分类号： G06F13/30

摘要： A method for arbitrating between direct memory access task requests, the method includes receiving multiple DMA task requests; the method is characterized by selecting a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks. A device that includes an interface, that is adapted to receive DMA task requests; the device is characterized by including an arbiter that is adapted to select a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks.

摘要翻译： 一种在直接存储器访问任务请求之间进行仲裁的方法，所述方法包括接收多个DMA任务请求; 该方法的特征在于响应于与DMA任务相关联的定时截止时间，从多个DMA任务请求中选择DMA任务请求。 一种包括适于接收DMA任务请求的接口的设备; 该装置的特征在于包括仲裁器，该仲裁器响应于与DMA任务相关联的定时截止时间，适于从多个DMA任务请求中选择DMA任务请求。

公开(公告)号：US20090172414A1

公开(公告)日：2009-07-02

申请号：US11993811

申请日：2005-06-22

申请人： Odi Dahan ,  Ori Goren ,  Yehuda Shvager

发明人： Odi Dahan ,  Ori Goren ,  Yehuda Shvager

IPC分类号： G06F21/00 ,  G06F12/14 ,  G06F11/00 ,  H04L9/06

CPC分类号： G06F21/85 ,  G06F21/72

摘要： A device that includes a first memory unit adapted to store encrypted instructions, a processor adapted to execute decrypted instructions, a second memory unit accessible by the processor, and a decryption unit. The device is characterized by including a key database and a key selection circuit, wherein the key selection circuit is adapted to select a selected decryption key from the key database for decrypting encrypted instructions. The selection is responsive to a fixed selection information stored within the integrated circuit and to received key selection information.A method that includes a stage of receiving encrypted instructions; and executing decrypted instructions by a processor. The method is characterized by receiving key selection information, selecting a selected decryption key out of a key database in response to fixed selection information and to the received key selection information, and decrypting encrypted instructions using the selected decryption key.

摘要翻译： 一种包括适于存储加密指令的第一存储器单元，适于执行解密指令的处理器，由所述处理器访问的第二存储器单元和解密单元的设备。 该设备的特征在于包括密钥数据库和密钥选择电路，其中密钥选择电路适于从密钥数据库中选择一个选择的解密密钥，用于解密加密的指令。 该选择响应存储在集成电路内的固定选择信息和接收的键选择信息。 一种方法，包括接收加密指令的阶段; 以及由处理器执行解密指令。 该方法的特征在于，接收密钥选择信息，响应于固定选择信息从密钥数据库中选择所选择的解密密钥和接收的密钥选择信息，以及使用所选择的解密密钥解密加密指令。

公开(公告)号：US08397081B2

公开(公告)日：2013-03-12

申请号：US11993811

申请日：2005-06-22

申请人： Odi Dahan ,  Ori Goren ,  Yehuda Shvager

发明人： Odi Dahan ,  Ori Goren ,  Yehuda Shvager

IPC分类号： G06F11/30

CPC分类号： G06F21/85 ,  G06F21/72

摘要： A device includes a first memory unit adapted to store encrypted instructions, a processor adapted to execute decrypted instructions, a second memory unit accessible by the processor, and a decryption unit. The device includes a key database and a key selection circuit, wherein the key selection circuit is adapted to select a selected decryption key from the key database for decrypting encrypted instructions. The selection is responsive to a fixed selection information stored within the integrated circuit and to received key selection information. A method includes a stage of receiving encrypted instructions; and executing decrypted instructions by a processor. The method includes receiving key selection information, selecting a selected decryption key out of a key database in response to fixed selection information and to the received key selection information, and decrypting encrypted instructions using the selected decryption key.

摘要翻译： 设备包括适于存储加密指令的第一存储器单元，适于执行解密指令的处理器，由处理器访问的第二存储器单元和解密单元。 所述设备包括密钥数据库和密钥选择电路，其中密钥选择电路适于从密钥数据库中选择所选择的解密密钥，以解密加密的指令。 该选择响应存储在集成电路内的固定选择信息和接收的键选择信息。 一种方法包括接收加密指令的阶段; 以及由处理器执行解密指令。 所述方法包括接收密钥选择信息，响应于固定选择信息从密钥数据库中选择所选择的解密密钥和接收到的密钥选择信息，以及使用所选择的解密密钥解密加密指令。

公开(公告)号：US20090216917A1

公开(公告)日：2009-08-27

申请号：US11994270

申请日：2005-06-30

申请人： Uri Shasha ,  Sagi Gurfinkel ,  Gilad Hassid ,  Eran Kahn ,  Yehuda Shvager

发明人： Uri Shasha ,  Sagi Gurfinkel ,  Gilad Hassid ,  Eran Kahn ,  Yehuda Shvager

IPC分类号： G06F13/30 ,  G06F12/00

CPC分类号： G06F13/30

摘要： A method for arbitrating between direct memory access task requests, the method includes receiving multiple DMA task requests; the method is characterized by selecting a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks. A device that includes an interface, that is adapted to receive DMA task requests; the device is characterized by including an arbiter that is adapted to select a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks.

摘要翻译： 一种在直接存储器访问任务请求之间进行仲裁的方法，所述方法包括接收多个DMA任务请求; 该方法的特征在于响应于与DMA任务相关联的定时截止时间，从多个DMA任务请求中选择DMA任务请求。 一种包括适于接收DMA任务请求的接口的设备; 该装置的特征在于包括仲裁器，该仲裁器响应于与DMA任务相关联的定时截止时间，适于从多个DMA任务请求中选择DMA任务请求。