DEVICE AND METHOD FOR SECURING SOFTWARE
    1.
    发明申请
    DEVICE AND METHOD FOR SECURING SOFTWARE 有权
    用于安全软件的设备和方法

    公开(公告)号:US20090172414A1

    公开(公告)日:2009-07-02

    申请号:US11993811

    申请日:2005-06-22

    CPC分类号: G06F21/85 G06F21/72

    摘要: A device that includes a first memory unit adapted to store encrypted instructions, a processor adapted to execute decrypted instructions, a second memory unit accessible by the processor, and a decryption unit. The device is characterized by including a key database and a key selection circuit, wherein the key selection circuit is adapted to select a selected decryption key from the key database for decrypting encrypted instructions. The selection is responsive to a fixed selection information stored within the integrated circuit and to received key selection information.A method that includes a stage of receiving encrypted instructions; and executing decrypted instructions by a processor. The method is characterized by receiving key selection information, selecting a selected decryption key out of a key database in response to fixed selection information and to the received key selection information, and decrypting encrypted instructions using the selected decryption key.

    摘要翻译: 一种包括适于存储加密指令的第一存储器单元,适于执行解密指令的处理器,由所述处理器访问的第二存储器单元和解密单元的设备。 该设备的特征在于包括密钥数据库和密钥选择电路,其中密钥选择电路适于从密钥数据库中选择一个选择的解密密钥,用于解密加密的指令。 该选择响应存储在集成电路内的固定选择信息和接收的键选择信息。 一种方法,包括接收加密指令的阶段; 以及由处理器执行解密指令。 该方法的特征在于,接收密钥选择信息,响应于固定选择信息从密钥数据库中选择所选择的解密密钥和接收的密钥选择信息,以及使用所选择的解密密钥解密加密指令。

    Device and method for securing software
    2.
    发明授权
    Device and method for securing software 有权
    用于保护软件的设备和方法

    公开(公告)号:US08397081B2

    公开(公告)日:2013-03-12

    申请号:US11993811

    申请日:2005-06-22

    IPC分类号: G06F11/30

    CPC分类号: G06F21/85 G06F21/72

    摘要: A device includes a first memory unit adapted to store encrypted instructions, a processor adapted to execute decrypted instructions, a second memory unit accessible by the processor, and a decryption unit. The device includes a key database and a key selection circuit, wherein the key selection circuit is adapted to select a selected decryption key from the key database for decrypting encrypted instructions. The selection is responsive to a fixed selection information stored within the integrated circuit and to received key selection information. A method includes a stage of receiving encrypted instructions; and executing decrypted instructions by a processor. The method includes receiving key selection information, selecting a selected decryption key out of a key database in response to fixed selection information and to the received key selection information, and decrypting encrypted instructions using the selected decryption key.

    摘要翻译: 设备包括适于存储加密指令的第一存储器单元,适于执行解密指令的处理器,由处理器访问的第二存储器单元和解密单元。 所述设备包括密钥数据库和密钥选择电路,其中密钥选择电路适于从密钥数据库中选择所选择的解密密钥,以解密加密的指令。 该选择响应存储在集成电路内的固定选择信息和接收的键选择信息。 一种方法包括接收加密指令的阶段; 以及由处理器执行解密指令。 所述方法包括接收密钥选择信息,响应于固定选择信息从密钥数据库中选择所选择的解密密钥和接收到的密钥选择信息,以及使用所选择的解密密钥解密加密指令。

    DEVICE HAVING REDUNDANT CORE AND A METHOD FOR PROVIDING CORE REDUNDANCY
    3.
    发明申请
    DEVICE HAVING REDUNDANT CORE AND A METHOD FOR PROVIDING CORE REDUNDANCY 审中-公开
    具有冗余核心的设备和提供核心冗余的方法

    公开(公告)号:US20100325481A1

    公开(公告)日:2010-12-23

    申请号:US12446409

    申请日:2006-10-20

    IPC分类号: G06F11/20

    摘要: A device and a method for providing core redundancy, the device includes: multiple cores; a core operability unit adapted to indicate an operability of each core out of the multiple cores; and a core control signal unit adapted to provide mapping signals that comprise virtual core to physical core mapping signals and physical core to virtual core mapping signals; wherein each core out of the multiple cores comprises at least one interrupt interface, and a crossbar interface which are responsive to at least one mapping signal.

    摘要翻译: 一种用于提供核心冗余的设备和方法,所述设备包括:多个核心; 核心可操作单元,其适于指示所述多个核心中的每个核心的可操作性; 以及核心控制信号单元,其适于提供包括虚拟核心到物理核心映射信号和物理核心到虚拟核心映射信号的映射信号; 其中所述多个核心中的每个核心包括响应于至少一个映射信号的至少一个中断接口和交叉开关接口。

    Apparatus, system and method for controlling packet data flow

    公开(公告)号:US10225196B2

    公开(公告)日:2019-03-05

    申请号:US14765841

    申请日:2013-02-15

    摘要: A system for use in nodes communicating over a CPRI (common public radio interface) allows each networking node in a daisychain configuration to seamlessly manage the control and management HDLC (high-speed data link control) channel for both uplink and downlink. The connection is kept alive through a soft reset flow. Received HDLC packets can be extracted for use by a local node. Locally generated packets can be inserted into the packet data stream at the datalink layer for onward transmission over the CPRI. The system arbitrates between the locally generated packet data held in a buffer in the local node and remote packet data received from a remote node and held in the local node in a first in first out buffer for onward transmission to a subsequent node after arbitration. Remote packet data is given priority.

    METHOD AND DEVICE FOR INTERFACING IN A MOBILE COMMUNICATION SYSTEM
    5.
    发明申请
    METHOD AND DEVICE FOR INTERFACING IN A MOBILE COMMUNICATION SYSTEM 有权
    用于在移动通信系统中接口的方法和设备

    公开(公告)号:US20160128040A1

    公开(公告)日:2016-05-05

    申请号:US14889485

    申请日:2013-05-29

    IPC分类号: H04W72/04 H04L27/233

    摘要: Interfacing according to a common public radio interface in a base station in a mobile communication system is described. The interfacing comprises a conversion process for rate-converting legacy data samples. First a predetermined number of the legacy data samples is converted to frequency samples in a frequency domain, then the frequency samples are zero padded to extend the frequency range according to a related sample rate of a 4G data format and then converted into a number of data samples of the related sample rate. The related sample rate is a multiplication of S/K times a basic frame rate of the 4G data format, S samples being allocated to K frames, K and S being integers and K being 8 or less. Advantageously large buffers for allocating a large number of legacy samples to 4G frames are avoided.

    摘要翻译: 描述了根据移动通信系统中的基站中的公共无线电接口的公共接口。 接口包括用于对传统数据样本进行速率转换的转换过程。 首先,将预定数量的遗留数据样本转换为频域中的频率采样,然后根据4G数据格式的相关采样率将频率采样零填充以扩展频率范围,然后转换成多个数据 相关采样率样本。 相关采样率是S / K乘以4G数据格式的基本帧速率,S个样本被分配给K个帧,K和S是整数,K是8或更小。 有利的是,避免了将大量遗留样本分配到4G帧的大型缓冲器。

    Device having priority upgrade mechanism capabilities and a method for updating priorities
    6.
    发明授权
    Device having priority upgrade mechanism capabilities and a method for updating priorities 有权
    具有优先级升级机制能力的设备和更新优先级的方法

    公开(公告)号:US08078781B2

    公开(公告)日:2011-12-13

    申请号:US12377806

    申请日:2006-08-23

    IPC分类号: G06F13/38

    CPC分类号: G06F13/364

    摘要: A device having priority update capabilities and a method for updating priorities, the method includes: receiving a request to update to a requested priority, priorities of transaction requests stored within a first sequence of pipeline stages that precede an arbiter; updating a priority level of a transaction request stored in the first sequence to the requested priority if the transaction request is priority upgradeable and if the requested priority is higher that a current priority of the transaction request; and arbitrating between transaction requests in response to priority attributes associated with the transaction requests.

    摘要翻译: 一种具有优先级更新功能的设备和一种用于更新优先级的方法,所述方法包括:接收对请求的优先级的请求,存储在仲裁器之前的流水线级的第一序列内存储的事务请求的优先级; 如果所述事务请求是优先级可升级的并且所请求的优先级高于所述事务请求的当前优先级,则将存储在所述第一序列中的事务请求的优先级更新为所请求的优先级; 以及响应于与所述事务请求相关联的优先级属性在事务请求之间进行仲裁。

    Method and apparatus for processing data flows

    公开(公告)号:US09635710B2

    公开(公告)日:2017-04-25

    申请号:US14776746

    申请日:2013-03-28

    IPC分类号: H04W4/00 H04W88/08

    CPC分类号: H04W88/085

    摘要: An apparatus for facilitating the re-distribution of processing load between a plurality of radio equipment controllers arranged in a daisy chain configuration on a Common Public Radio Interface. The apparatus may be included in each REC and has two framers which may co-operate to forward IQ data of antenna carriers received on a downlink from a preceding REC to a subsequent REC in the chain and a DMA module or channel which can read IQ data from a system memory for onward transmission. In a re-allocation mode, the framer may be reconfigured so that an AxC initially allocated to a preceding REC for processing may be instead, accessed by a second (usually redundant) transmit DMA module included in the apparatus from system memory and transferred to the framer for onward transmission.

    ELECTRONIC AND MANUAL LOCK ASSEMBLY
    10.
    发明申请
    ELECTRONIC AND MANUAL LOCK ASSEMBLY 有权
    电子和手动锁定装置

    公开(公告)号:US20120324967A1

    公开(公告)日:2012-12-27

    申请号:US13166153

    申请日:2011-06-22

    申请人: Ori Goren Amir Katz

    发明人: Ori Goren Amir Katz

    IPC分类号: E05B47/00 E05B37/00 E05B23/00

    摘要: An electronic and manual lock assembly having a lock housing, a mechanical lock, an electric motor, and a shackle having a pair of legs. The shackle can be unlocked relative to the housing by having one leg pivotally connected with the housing and the other leg rotated out of the housing. The lock includes a first stop member that prevents one leg from being rotated out of the housing. The first stop member is moveable as a result of unlocking the mechanical lock. The lock includes a second stop member that prevents one of the legs from being rotated out of the lock housing and is moveable as a result of operating the electric motor. The first stop member and the second stop member are independently moveable by the mechanical lock and the electric motor.

    摘要翻译: 一种具有锁定壳体,机械锁定器,电动马达和具有一对腿部的钩环的电子和手动锁定组件。 通过使一个腿与壳体枢转地连接并且另一个腿部旋转离开壳体,该钩环可以相对于壳体解锁。 该锁包括防止一条腿从壳体旋转出来的第一阻挡构件。 由于解锁机械锁,第一个停止部件可移动。 该锁包括第二止挡构件,其阻止腿中的一个从锁壳外旋出并且由于操作电动机而可移动。 第一止挡件和第二挡块可通过机械锁和电动马达独立地移动。