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    Level shifter circuit
    3.
    发明授权
    Level shifter circuit 失效
    电平移位电路

    公开(公告)号：US5659258A

    公开(公告)日：1997-08-19

    申请号：US365471

    申请日：1994-12-27

    申请人： Tetsuya Tanabe ,  Satoru Tanoi ,  Yasuhiro Tanaka

    发明人： Tetsuya Tanabe ,  Satoru Tanoi ,  Yasuhiro Tanaka

    IPC分类号： G06F3/00 ,  H03K3/356 ,  H03K5/02 ,  H03K19/0185 ,  H03K19/0948

    CPC分类号： H03K3/356017 ,  H03K3/35606 ,  H03K3/356113

    摘要： There is provided a level shifter circuit which operates such that when the potential of the input signal changes from the ground potential to the first power source potential, the third transistor turns to be ON, and the fifth transistor turns to be OFF. On this instance, since the potential of the output signal is higher than the first power source potential, the second electrode of the first transistor is initiated to be charged up through the third and the fourth transistors. After that, the potential of the output signal falls down when the eighth transistor turns to be ON state. Since the potential of the second electrode of the first transistor has been charged up, the second transistor quickly turns to be OFF state so that the rush current is reduced flown from the second power source potential to the ground potential. When the potential of the output signal drops down enough, the fourth transistor turns to be OFF state so that the rush current flown from the second power source potential to the first power source potential is prevented.

    摘要翻译： 提供了一种电平移位器电路，其操作使得当输入信号的电位从地电位变为第一电源电位时，第三晶体管变为导通，第五晶体管变为截止。 在这种情况下，由于输出信号的电位高于第一电源电位，所以第一晶体管的第二电极开始通过第三和第四晶体管充电。 此后，当第八晶体管变为导通状态时，输出信号的电位下降。 由于第一晶体管的第二电极的电位已经被充电，所以第二晶体管迅速转为截止状态，使得冲击电流从第二电源电位流到地电势减小。 当输出信号的电位下降足够时，第四晶体管变为OFF状态，从而防止从第二电源电位流到第一电源电位的冲击电流。

    Semiconductor memory
    8.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US5875148A

    公开(公告)日：1999-02-23

    申请号：US454118

    申请日：1995-06-02

    申请人： Yasuhiro Tanaka ,  Satoru Tanoi

    发明人： Yasuhiro Tanaka ,  Satoru Tanoi

    IPC分类号： G11C8/08 ,  G11C8/14 ,  G11C11/408 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00

    CPC分类号： H01L27/10897 ,  G11C11/4085 ,  G11C8/08 ,  G11C8/14 ,  H01L27/10891

    摘要： A plurality of memory cell arrays each having a plurality of memory cells and a plurality of word lines the word lines are driven by drive circuits which share the driving operation, and permit reading out from and writing into the memory cells connected to the word lines WL to be driven. These drive circuits are respectively connected to main word lines WLO, which are driven by decoding the entered address information in a decoding circuit whereby the drive circuits are driven. Since the main word lines WLO are formed with a third metal wiring layer, a wiring of the word lines can be formed with a gate wiring layer of a transistor and a first metal wiring layer and wiring of a line control circuit can be formed with a second metal wiring layer which intersects the word lines thereby reducing delay operation of the memory.

    摘要翻译： PCT PCT / JP94 / 00115 Sec。 371日期：1995年6月2日 102（e）1995年6月2日PCT 1994年1月28日PCT PCT。 出版物WO94 / 17554 日期1994年8月4日多个存储单元阵列，每个存储单元阵列具有多个存储单元和多个字线，字线由共享驱动操作的驱动电路驱动，并且允许从连接的存储单元读出和写入 到要驱动的字线WL。 这些驱动电路分别连接到主字线WLO，它们通过在驱动电路驱动的解码电路中解码输入的地址信息来驱动。 由于主字线WLO由第三金属布线层形成，所以字线的布线可以由晶体管的栅极布线层和第一金属布线层形成，并且线路控制电路的布线可以形成有 与字线相交的第二金属布线层，从而减少存储器的延迟操作。

    Semiconductor memory with built-in cache
    9.
    发明授权
    Semiconductor memory with built-in cache 失效
    半导体内存具有内置缓存

    公开(公告)号：US5596521A

    公开(公告)日：1997-01-21

    申请号：US365970

    申请日：1994-12-29

    申请人： Yasuhiro Tanaka ,  Tetsuya Tanabe ,  Satoru Tanoi

    发明人： Yasuhiro Tanaka ,  Tetsuya Tanabe ,  Satoru Tanoi

    IPC分类号： G06F12/08 ,  G11C7/10 ,  G11C11/4096 ,  G11C15/04 ,  G11C15/00

    CPC分类号： G11C7/106 ,  G06F12/0893 ,  G11C11/4096 ,  G11C15/04 ,  G11C15/043 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078 ,  G11C2207/2245

    摘要： A semiconductor memory device has memory cells for storing data, sense amplifiers for amplifying the stored data, and cache cells in which the amplified data can be placed for quick recall. The cache cells can continue to hold data during memory-cell refresh cycles, permitting the cached data to be accessed quickly afterward. The cache cells may be coupled to column data lines that can be disconnected from the sense amplifiers, enabling memory cells to be refreshed while cache access is in progress. Write buffers may be provided so that when cache data are replaced, the old cache data can be copied back to the memory cells while the new cache data are being accessed.

    摘要翻译： 半导体存储器件具有用于存储数据的存储器单元，用于放大所存储的数据的读出放大器，以及可放置放大数据以用于快速调用的高速缓存单元。 高速缓存单元可以在存储单元刷新周期期间继续保持数据，从而允许快速访问缓存的数据。 高速缓存单元可以耦合到可以从读出放大器断开的列数据线，使得能够刷新存储器单元，同时缓存访问正在进行。 可以提供写入缓冲器，使得当高速缓存数据被替换时，旧的高速缓存数据可以被复制回存储器单元，同时正在访问新的高速缓存数据。

    Dynamic random access memory (DRAM) with cache and tag
    10.
    发明授权
    Dynamic random access memory (DRAM) with cache and tag 失效
    具有缓存和标签的动态随机存取存储器（DRAM）

    公开(公告)号：US5577223A

    公开(公告)日：1996-11-19

    申请号：US297450

    申请日：1994-08-29

    申请人： Satoru Tanoi ,  Yasuhiro Tanaka ,  Tetsuya Tanabe

    发明人： Satoru Tanoi ,  Yasuhiro Tanaka ,  Tetsuya Tanabe

    IPC分类号： G06F12/08 ,  G11C11/401 ,  G11C11/408 ,  G06F12/00

    CPC分类号： G11C11/4087 ,  G06F12/0893

    摘要： A dynamic RAM having a TAG address holding circuit in a TAG block in correspondence with one of a plurality of sub-arrays to hold the lower bits of an X (row) address. A block control circuit in the TAG block determines a "Hit" or "Miss" in accordance with the held address and a new X address in response to the sub-address and outputs a TAG determination signal. In response to the TAG judgment signal, a sub-array control circuit transfers a signal for access to the TAG block and a column sense amplifier. The column sense amplifier is utilized as a cache and data latched in the column sense amplifier are read out on a data bus when a "Hit" is determined.

    摘要翻译： 一种具有TAG块中的TAG地址保持电路的动态RAM，其与多个子阵列中的一个子阵列对应以保持X（行）地址的低位。 TAG块中的块控制电路根据所保存的地址确定“命中”或“小号”，并响应于子地址确定新的X地址并输出TAG确定信号。 响应于TAG判断信号，子阵列控制电路传送用于访问TAG块和列读出放大器的信号。 当确定“命中”时，列读出放大器用作高速缓存，并且锁存在列读出放大器中的数据在数据总线上读出。