公开(公告)号：US20120105110A1

公开(公告)日：2012-05-03

申请号：US13200024

申请日：2011-09-15

申请人： Yasuo Kitayama ,  Hiroyuki Demura ,  Naoki Onishi

发明人： Yasuo Kitayama ,  Hiroyuki Demura ,  Naoki Onishi

IPC分类号： H03B21/00 ,  H03L7/06

CPC分类号： H03B21/00 ,  H03G1/0058 ,  H03G3/30 ,  H03L5/00

摘要： To provide, in a frequency synthesizer including: a variable attenuator provided at a subsequent stage of a voltage controlled oscillator; a detector; and a control unit outputting a control voltage for adjusting an attenuation amount of the variable attenuator via a digital/analog converter in accordance with a detection voltage, a technology with which a spurious due to a change in an output of the digital/analog converter can be suppressed. A low-pass filter is provided between an output side of a digital/analog converter and a variable attenuator to cut a frequency component corresponding to an overshoot generated when an output of the digital/analog converter is changed. Further, a period of time from when a control unit outputs a control voltage to when it reads a signal level detected by a detector is set to a period of time longer than a time constant of the low-pass filter determined by a cut-off frequency of the low-pass filter so that no influence is exerted on an operation of automatically controlling the signal level.

摘要翻译： 提供一种频率合成器，包括：设置在压控振荡器的后续级的可变衰减器; 检测器 以及控制单元，其根据检测电压输出用于经由数字/模拟转换器调整可变衰减器的衰减量的控制电压，由于数字/模拟转换器的输出的变化引起的寄生的杂散技术 被压制 在数字/模拟转换器的输出侧和可变衰减器之间提供低通滤波器，以便在数字/模拟转换器的输出改变时产生的过冲相应的剪切频率分量。 此外，从控制单元输出控制电压到读取检测器检测到的信号电平的时间段被设置为比由截止器确定的低通滤波器的时间常数更长的时间段 低通滤波器的频率，从而不会对自动控制信号电平的操作产生影响。

公开(公告)号：US20100308929A1

公开(公告)日：2010-12-09

申请号：US12801421

申请日：2010-06-08

申请人： Yasuo Kitayama ,  Hiroyuki Demura

发明人： Yasuo Kitayama ,  Hiroyuki Demura

IPC分类号： H03B5/12

CPC分类号： H03B5/1231 ,  H03B5/1203 ,  H03B5/1237

摘要： A low noise voltage-controlled oscillating circuit which can remove a power source noise to improve low frequency noise characteristics is disclosed. A capacitor C11 is provided between a base of a driving transistor Q1 and GND, whereby a low frequency noise input into the base can be removed. As the driving transistor Q1, a transistor having a low hFE is used, whereby the low frequency noise input from a power source can be removed. A coil L3 is provided on the emitter side of an oscillating transistor Q2, whereby broadband frequency characteristics can be obtained to improve phase noise frequency characteristics. On the emitter side of the oscillating transistor Q2, a resonance frequency in a resonant circuit having a capacitor C7 and the coil L3 is set near the center of a VCO oscillation frequency band, whereby it is possible to obtain the oscillation frequency which is not easily influenced by the noise.

摘要翻译： 公开了一种能够消除电源噪声以改善低频噪声特性的低噪声压控振荡电路。 电容器C11设置在驱动晶体管Q1和GND的基极之间，从而可以去除输入到基极的低频噪声。 作为驱动晶体管Q1，使用具有低hFE的晶体管，由此能够去除从电源输入的低频噪声。 在振荡晶体管Q2的发射极侧设置有线圈L3，由此能够获得宽带频率特性以提高相位噪声频率特性。 在振荡晶体管Q2的发射极侧，具有电容器C7和线圈L3的谐振电路中的谐振频率设定在VCO振荡频带的中心附近，由此可以获得不容易的振荡频率 受噪音影响。

公开(公告)号：US08633735B2

公开(公告)日：2014-01-21

申请号：US13200024

申请日：2011-09-15

申请人： Yasuo Kitayama ,  Hiroyuki Demura ,  Naoki Onishi

发明人： Yasuo Kitayama ,  Hiroyuki Demura ,  Naoki Onishi

IPC分类号： H03B21/00

CPC分类号： H03B21/00 ,  H03G1/0058 ,  H03G3/30 ,  H03L5/00

摘要： To provide, in a frequency synthesizer including: a variable attenuator provided at a subsequent stage of a voltage controlled oscillator; a detector; and a control unit outputting a control voltage for adjusting an attenuation amount of the variable attenuator via a digital/analog converter in accordance with a detection voltage, a technology with which a spurious due to a change in an output of the digital/analog converter can be suppressed. A low-pass filter is provided between an output side of a digital/analog converter and a variable attenuator to cut a frequency component corresponding to an overshoot generated when an output of the digital/analog converter is changed. Further, a period of time from when a control unit outputs a control voltage to when it reads a signal level detected by a detector is set to a period of time longer than a time constant of the low-pass filter determined by a cut-off frequency of the low-pass filter so that no influence is exerted on an operation of automatically controlling the signal level.

摘要翻译： 提供一种频率合成器，包括：设置在压控振荡器的后续级的可变衰减器; 检测器 以及控制单元，其根据检测电压输出用于经由数字/模拟转换器调整可变衰减器的衰减量的控制电压，由于数字/模拟转换器的输出的变化引起的寄生的杂散技术 被压制 在数字/模拟转换器的输出侧和可变衰减器之间提供低通滤波器，以便在数字/模拟转换器的输出改变时产生的过冲相应的剪切频率分量。 此外，从控制单元输出控制电压到读取检测器检测到的信号电平的时间段被设置为比由截止器确定的低通滤波器的时间常数更长的时间段 低通滤波器的频率，从而不会对自动控制信号电平的操作产生影响。

公开(公告)号：US08149069B2

公开(公告)日：2012-04-03

申请号：US12801421

申请日：2010-06-08

申请人： Yasuo Kitayama ,  Hiroyuki Demura

发明人： Yasuo Kitayama ,  Hiroyuki Demura

IPC分类号： H03B5/08

CPC分类号： H03B5/1231 ,  H03B5/1203 ,  H03B5/1237

摘要： A low noise voltage-controlled oscillating circuit which can remove a power source noise to improve low frequency noise characteristics is disclosed. A capacitor C11 is provided between a base of a driving transistor Q1 and GND, whereby a low frequency noise input into the base can be removed. As the driving transistor Q1, a transistor having a low hFE is used, whereby the low frequency noise input from a power source can be removed. A coil L3 is provided on the emitter side of an oscillating transistor Q2, whereby broadband frequency characteristics can be obtained to improve phase noise frequency characteristics. On the emitter side of the oscillating transistor Q2, a resonance frequency in a resonant circuit having a capacitor C7 and the coil L3 is set near the center of a VCO oscillation frequency band, whereby it is possible to obtain the oscillation frequency which is not easily influenced by the noise.

摘要翻译： 公开了一种能够消除电源噪声以改善低频噪声特性的低噪声压控振荡电路。 电容器C11设置在驱动晶体管Q1和GND的基极之间，从而可以去除输入到基极的低频噪声。 作为驱动晶体管Q1，使用具有低hFE的晶体管，由此能够去除从电源输入的低频噪声。 在振荡晶体管Q2的发射极侧设置有线圈L3，由此能够获得宽带频率特性以提高相位噪声频率特性。 在振荡晶体管Q2的发射极侧，具有电容器C7和线圈L3的谐振电路中的谐振频率设定在VCO振荡频带的中心附近，由此可以获得不容易的振荡频率 受噪音影响。

公开(公告)号：US07791416B2

公开(公告)日：2010-09-07

申请号：US12222530

申请日：2008-08-11

申请人： Hiroki Kimura ,  Tsukasa Kobata ,  Yasuo Kitayama ,  Naoki Onishi

发明人： Hiroki Kimura ,  Tsukasa Kobata ,  Yasuo Kitayama ,  Naoki Onishi

IPC分类号： H03B1/00 ,  H03L7/06 ,  H03L7/093

CPC分类号： H03L7/093 ,  H03L7/18

摘要： A PLL circuit which can absorb variation of phase noise characteristic due to temperature and individual difference and has a phase noise suppression characteristic stable in a wide frequency band is provided. The PLL circuit comprises, at the succeeding stage, a first register for storing a first parameter for controlling the loop gain, a first multiplier for multiplying the output of the phase comparator by a first parameter, a second register for storing a second parameter for controlling the response characteristic, a second multiplier for multiplying the output of the first multiplier by a second parameter, and a CPU for setting optimum parameters in the first and second registers depending on the use frequency band, the ambient temperature, and the device individual difference. By controlling the loop gain and the response characteristic to optimum values, a good suppression characteristic in a wide frequency band is achieved.

摘要翻译： 提供一种可以吸收由于温度和个体差异引起的相位噪声特性的变化并且具有在宽频带中稳定的相位噪声抑制特性的PLL电路。 PLL电路在后续阶段包括用于存储用于控制环路增益的第一参数的第一寄存器，用于将相位比较器的输出乘以第一参数的第一乘法器，用于存储用于控制的第二参数的第二寄存器 响应特性，用于将第一乘法器的输出乘以第二参数的第二乘法器和用于根据使用频带，环境温度和设备个体差异来设置第一和第二寄存器中的最佳参数的CPU。 通过将环路增益和响应特性控制为最佳值，实现了宽频带中良好的抑制特性。

公开(公告)号：US20090021312A1

公开(公告)日：2009-01-22

申请号：US12222530

申请日：2008-08-11

申请人： Hiroki Kimura ,  Tsukasa Kobata ,  Yasuo Kitayama ,  Naoki Onishi

发明人： Hiroki Kimura ,  Tsukasa Kobata ,  Yasuo Kitayama ,  Naoki Onishi

IPC分类号： H03L7/099

CPC分类号： H03L7/093 ,  H03L7/18

摘要： It has been difficult that conventional PLL circuits have a suppression characteristic of suppressing the phase noise which is free of variation due to temperature and individual difference and stable in a wide frequency band. The present invention provides a PLL circuit which can absorb variation of phase noise characteristic due to temperature and individual difference and has a phase noise suppression characteristic stable in a wide frequency band. The PLL circuit comprises, at the succeeding stage, a first register for storing a first parameter for controlling the loop gain, a first multiplier for multiplying the output of the phase comparator by a first parameter, a second register for storing a second parameter for controlling the response characteristic, a second multiplier for multiplying the output of the first multiplier by a second parameter, and a CPU for setting optimum parameters in the first and second registers depending on the use frequency band, the ambient temperature, and the device individual difference. By controlling the loop gain and the response characteristic to optimum values, a good suppression characteristic in a wide frequency band is achieved.

摘要翻译： 传统的PLL电路难以抑制由于温度和个体差异而没有变化并且在宽频带中稳定的相位噪声的抑制特性。 本发明提供一种可以吸收由于温度和个体差异引起的相位噪声特性的变化的PLL电路，并且具有在宽频带中稳定的相位噪声抑制特性。 PLL电路在后续阶段包括用于存储用于控制环路增益的第一参数的第一寄存器，用于将相位比较器的输出乘以第一参数的第一乘法器，用于存储用于控制的第二参数的第二寄存器 响应特性，用于将第一乘法器的输出乘以第二参数的第二乘法器和用于根据使用频带，环境温度和设备个体差异来设置第一和第二寄存器中的最佳参数的CPU。 通过将环路增益和响应特性控制为最佳值，实现了宽频带中良好的抑制特性。

公开(公告)号：US20090039973A1

公开(公告)日：2009-02-12

申请号：US12219452

申请日：2008-07-22

申请人： Yasuo Kitayama ,  Hiroki Kimura ,  Naoki Onishi ,  Nobuo Tsukamoto

发明人： Yasuo Kitayama ,  Hiroki Kimura ,  Naoki Onishi ,  Nobuo Tsukamoto

IPC分类号： H03B5/08

CPC分类号： H03L7/093 ,  H03L1/026 ,  H03L7/107 ,  H03L7/1075 ,  H03L7/18 ,  H03L7/189

摘要： A VCO driving circuit and a frequency synthesizer wherein the impedance viewed from a VCO control terminal is reduced to prevent the VCO phase noise characteristic from degrading. A VCO driving circuit and a frequency synthesizer having the VCO driving circuit, which comprises a coarse adjustment DAC that receives a digital data, which has a coarse adjustment frequency, to output an analog signal; a fine adjustment DAC that receives a digital data, which has a fine adjustment frequency, to output an analog signal; a low response speed LPF5 that removes noise from the output signal from the coarse adjustment DAC and then provides the resultant signal as an input to a VCO control terminal; a high response speed LPF7 that converts the output signal from the fine adjustment DAC to a voltage, thereby smoothing the signal; a resistor that connects an input stage of the LPF5 to that of the LPF7; and a capacitor used for providing a capacitive coupling such that the output of the LPF7 is added to that of the LPF5.

摘要翻译： VCO驱动电路和频率合成器，其中从VCO控制端子观察的阻抗减小，以防止VCO相位噪声特性降级。 VCO驱动电路和具有VCO驱动电路的频率合成器，其包括具有粗略调整频率的接收数字数据的粗调DAC以输出模拟信号; 微调DAC，其接收具有微调频率的数字数据，以输出模拟信号; 低响应速度LPF5，其从粗调DAC输出信号中去除噪声，然后将所得到的信号作为输入提供给VCO控制端; 高响应速度LPF7，其将来自微调DAC的输出信号转换为电压，从而平滑信号; 将LPF5的输入级与LPF7的输入级连接的电阻; 以及用于提供电容耦合的电容器，使得LPF7的输出被添加到LPF5的输出。

公开(公告)号：US07893774B2

公开(公告)日：2011-02-22

申请号：US12826236

申请日：2010-06-29

申请人： Yasuo Kitayama ,  Hiroki Kimura ,  Naoki Onishi ,  Nobuo Tsukamoto

发明人： Yasuo Kitayama ,  Hiroki Kimura ,  Naoki Onishi ,  Nobuo Tsukamoto

IPC分类号： H03L7/085 ,  H03L1/02

CPC分类号： H03L7/093 ,  H03L1/026 ,  H03L7/107 ,  H03L7/1075 ,  H03L7/18 ,  H03L7/189

摘要： A VCO driving circuit and a frequency synthesizer wherein the impedance viewed from a VCO control terminal is reduced to prevent the VCO phase noise characteristic from degrading. A VCO driving circuit and a frequency synthesizer having the VCO driving circuit, which comprises a coarse adjustment DAC that receives a digital data, which has a coarse adjustment frequency, to output an analog signal; a fine adjustment DAC that receives a digital data, which has a fine adjustment frequency, to output an analog signal; a low response speed LPF5 that removes noise from the output signal from the coarse adjustment DAC and then provides the resultant signal as an input to a VCO control terminal; a high response speed LPF7 that converts the output signal from the fine adjustment DAC to a voltage, thereby smoothing the signal; a resistor that connects an input stage of the LPF5 to that of the LPF7; and a capacitor used for providing a capacitive coupling such that the output of the LPF7 is added to that of the LPF5.

摘要翻译： VCO驱动电路和频率合成器，其中从VCO控制端子观察的阻抗减小，以防止VCO相位噪声特性降级。 VCO驱动电路和具有VCO驱动电路的频率合成器，其包括具有粗略调整频率的接收数字数据的粗调DAC以输出模拟信号; 微调DAC，其接收具有微调频率的数字数据，以输出模拟信号; 低响应速度LPF5，其从粗调DAC输出信号中去除噪声，然后将所得到的信号作为输入提供给VCO控制端; 高响应速度LPF7，其将来自微调DAC的输出信号转换为电压，从而平滑信号; 将LPF5的输入级与LPF7的输入级连接的电阻; 以及用于提供电容耦合的电容器，使得LPF7的输出被添加到LPF5的输出。

公开(公告)号：US07821344B2

公开(公告)日：2010-10-26

申请号：US12219452

申请日：2008-07-22

申请人： Yasuo Kitayama ,  Hiroki Kimura ,  Naoki Onishi ,  Nobuo Tsukamoto

发明人： Yasuo Kitayama ,  Hiroki Kimura ,  Naoki Onishi ,  Nobuo Tsukamoto

IPC分类号： H03L7/085 ,  H03L1/02

CPC分类号： H03L7/093 ,  H03L1/026 ,  H03L7/107 ,  H03L7/1075 ,  H03L7/18 ,  H03L7/189

摘要： A VCO driving circuit and a frequency synthesizer wherein the impedance viewed from a VCO control terminal is reduced to prevent the VCO phase noise characteristic from degrading. A VCO driving circuit and a frequency synthesizer having the VCO driving circuit, which comprises a coarse adjustment DAC that receives a digital data, which has a coarse adjustment frequency, to output an analog signal; a fine adjustment DAC that receives a digital data, which has a fine adjustment frequency, to output an analog signal; a low response speed LPF5 that removes noise from the output signal from the coarse adjustment DAC and then provides the resultant signal as an input to a VCO control terminal; a high response speed LPF7 that converts the output signal from the fine adjustment DAC to a voltage, thereby smoothing the signal; a resistor that connects an input stage of the LPF5 to that of the LPF7; and a capacitor used for providing a capacitive coupling such that the output of the LPF7 is added to that of the LPF5.

摘要翻译： VCO驱动电路和频率合成器，其中从VCO控制端子观察的阻抗减小，以防止VCO相位噪声特性降级。 VCO驱动电路和具有VCO驱动电路的频率合成器，其包括具有粗略调整频率的接收数字数据的粗调DAC以输出模拟信号; 微调DAC，其接收具有微调频率的数字数据，以输出模拟信号; 低响应速度LPF5，其从粗调DAC输出信号中去除噪声，然后将所得到的信号作为输入提供给VCO控制端; 高响应速度LPF7，其将来自微调DAC的输出信号转换为电压，从而平滑信号; 将LPF5的输入级与LPF7的输入级连接的电阻; 以及用于提供电容耦合的电容器，使得LPF7的输出被添加到LPF5的输出。

公开(公告)号：US07656208B2

公开(公告)日：2010-02-02

申请号：US11812520

申请日：2007-06-19

申请人： Hiroki Kimura ,  Tsukasa Kobata ,  Yasuo Kitayama ,  Naoki Onishi

发明人： Hiroki Kimura ,  Tsukasa Kobata ,  Yasuo Kitayama ,  Naoki Onishi

IPC分类号： H03L7/06

CPC分类号： H03L7/18 ,  H03L7/085

摘要： A digitally controlled PLL oscillation circuit has a VCO, a frequency divider, a reference oscillation circuit, an A/D converter, a phase comparator, a digital filter, a D/A converter, and an analog filter. A reference signal supplied from the reference oscillation circuit is output through a narrow-band crystal filter (MCF) to the A/D converter to cancel noise, jitter and a spurious wave included in the reference signal, making it possible to prevent the phase noise characteristic and spurious characteristic of a VCO output from being degraded.

摘要翻译： 数字控制PLL振荡电路具有VCO，分频器，参考振荡电路，A / D转换器，相位比较器，数字滤波器，D / A转换器和模拟滤波器。 从参考振荡电路提供的参考信号通过窄带晶体滤波器（MCF）输出到A / D转换器，以消除参考信号中包含的噪声，抖动和寄生波，从而可以防止相位噪声 VCO输出的特性和寄生特性降低。