公开(公告)号：US4924469A

公开(公告)日：1990-05-08

申请号：US152824

申请日：1988-02-05

申请人： Kiichiro Tamaru ,  Koichi Tanaka ,  Akira Kanuma ,  Yasuo Yamada

发明人： Kiichiro Tamaru ,  Koichi Tanaka ,  Akira Kanuma ,  Yasuo Yamada

IPC分类号： G06F11/22 ,  G06F11/267

CPC分类号： G06F11/2226 ,  G06F2201/83

摘要： In a system including LSIs, the signature register used for self-testing the LSI functions is assigned to one register accessible by a machine instruction. The signature is calculated in the self-test operation, and the calculation result is updated depending on the result from the execution of the machine instruction. With the above technical idea, the test function for the LSI function is available not only for the test mode, but also for the normal operation. This simplifies the self-test program for testing the functions of the application system.

摘要翻译： 在包括LSI的系统中，用于对LSI功能进行自检的签名寄存器被分配给可由机器指令访问的一个寄存器。 在自检操作中计算签名，并根据执行机器指令的结果更新计算结果。 通过上述技术思想，LSI功能的测试功能不仅可以用于测试模式，还可用于正常运行。 这简化了用于测试应用系统功能的自检程序。

公开(公告)号：US5325513A

公开(公告)日：1994-06-28

申请号：US870758

申请日：1992-04-20

申请人： Koichi Tanaka ,  Kiichiro Tamaru ,  Akira Kanuma ,  Yasuo Yamada

发明人： Koichi Tanaka ,  Kiichiro Tamaru ,  Akira Kanuma ,  Yasuo Yamada

IPC分类号： G06F13/16 ,  G06F1/04

CPC分类号： G06F13/1694

摘要： In a data processing apparatus, when making an access to a specific object to be accessed, the data processor supplies an access control signal to a plurality of control signal generators. The data processor further supplies accessed object type data to the accessed object type determining circuit. The determining circuit determines the type of the accessed object on the basis of the accessed object type data, and selectively drives the control signal generator corresponding to the accessed object. The control signal generator driven converts the access control signal into a control signal adapted for the accessed object. An address signal and data are transferred between the specific accessed object supplied with this control signal and the data processor via the address bus and data bus.

摘要翻译： 在数据处理装置中，当访问要访问的特定对象时，数据处理器向多个控制信号发生器提供访问控制信号。 数据处理器还将访问的对象类型数据提供给所访问的对象类型确定电路。 确定电路基于所访问的对象类型数据来确定所访问对象的类型，并且选择性地驱动对应于被访问对象的控制信号发生器。 控制信号发生器驱动将访问控制信号转换成适合被访问对象的控制信号。 地址信号和数据通过地址总线和数据总线在与该控制信号提供的特定访问对象和数据处理器之间传送。

公开(公告)号：US5276812A

公开(公告)日：1994-01-04

申请号：US759202

申请日：1991-09-11

申请人： Yasuo Yamada ,  Akira Kanuma ,  Kiichiro Tamaru ,  Koichi Tanaka

发明人： Yasuo Yamada ,  Akira Kanuma ,  Kiichiro Tamaru ,  Koichi Tanaka

IPC分类号： G11C7/10 ,  G11C8/00 ,  G11C8/12 ,  G06F12/00

CPC分类号： G11C7/1006 ,  G11C7/1021 ,  G11C8/00 ,  G11C8/12

摘要： In an address multiplexing apparatus for multiplexing address data to be supplied to 64K bit, 256K bit, and 1M bit DRAMs, upon multiplexing of address data, input address data of 20 bits are classified into two groups, i.e., the lower 16 bits and the upper 4 bits. The lower 16-bit group is multiplexed so that the upper 8 bits serve as row address data, and the remaining lower 8 bits serve as column address data. In the upper 4-bit group, adjacent bits are multiplexed. The apparatus can be commonly used for the three memories having different capacities with the simple circuit arrangement, and page mode access can be executed.

摘要翻译： 在地址多路复用装置中，对要提供给64K位，256K位和1M位DRAM的地址数据进行复用，在地址数据复用时，将20位的输入地址数据分为两组，即低16位和 高4位。 低16位组被复用，使得高8位用作行地址数据，而剩余的低8位用作列地址数据。 在高4位组中，相邻位被复用。 该装置可以通过简单的电路装置通常用于具有不同容量的三个存储器，并且可以执行页面模式访问。

公开(公告)号：US06223279B1

公开(公告)日：2001-04-24

申请号：US08482792

申请日：1995-06-07

申请人： Akira Nishimura ,  Sunao Ogawa ,  Yasuo Yamada ,  Akira Kanuma

发明人： Akira Nishimura ,  Sunao Ogawa ,  Yasuo Yamada ,  Akira Kanuma

IPC分类号： G06F1500

CPC分类号： G06F15/7842 ,  G06F9/462

摘要： A single chip microcomputer comprises a central processing unit (CPU) 2, a on-chip RAM 3, a on-chip ROM 5, a first bus DBUS for connecting the CPU, RAM, and ROM with one another and transferring data between them, a second bus ABUS for passing address data corresponding to the data passed through the first bus, a third bus SDBUS for connecting the CPU 2 with the RAM 3 and transferring data between them, the number of bits of the third bus SDBUS being larger than that of the first bus DBUS, and a fourth bus BABUS for connecting the CPU 2 with the RAM 3 and passing address data corresponding to the data passed through the third bus SDBUS. The CPU 2 has a data memory RF serving as general purpose registers for providing internal data to the third bus SDBUS, and a bank specifying register BP for holding positional data of a mapping region in the RAM 3 where the contents of the data memory RF are mapped and providing the positional data to the fourth bus BABUS. The RAM 3 has a memory cell array 31, a bank address control circuit 35 connected to the fourth bus BABUS, for generating a real address according to the contents of the bank specifying register BP (BP0, BP1), and a selection circuit 37 for selecting the real address generated by the bank address control circuit 35, or the address provided through the second bus ABUS.

摘要翻译： 单片微计算机包括中央处理单元（CPU）2，片上RAM 3，片上ROM 5，用于将CPU，RAM和ROM相互连接并在它们之间传送数据的第一总线DBUS， 用于传送与通过第一总线通过的数据相对应的地址数据的第二总线ABUS，用于将CPU2与RAM3连接并在它们之间传送数据的第三总线SDBUS，第三总线SDBUS的位数大于 的第一总线DBUS和第四总线BABUS，用于将CPU 2与RAM 3连接，并且传递与通过第三总线SDBUS通过的数据相对应的地址数据。 CPU2具有用作向第三总线SDBUS提供内部数据的通用寄存器的数据存储器RF以及用于保持RAM 3中的映射区域的位置数据的存储体指定寄存器BP，其中数据存储器RF的内容为 映射并将位置数据提供给第四总线BABUS。 RAM3具有存储单元阵列31，与第四总线BABUS连接的存储体地址控制电路35，用于根据存储体指定寄存器BP（BP0，BP1）的内容生成实际地址，以及选择电路37， 选择由存储体地址控制电路35生成的实际地址，或通过第二总线ABUS提供的地址。

公开(公告)号：US5557766A

公开(公告)日：1996-09-17

申请号：US964142

申请日：1992-10-21

申请人： Nobuhiro Takiguchi ,  Soichi Kawasaki ,  Yasuo Yamada ,  Akira Kanuma

发明人： Nobuhiro Takiguchi ,  Soichi Kawasaki ,  Yasuo Yamada ,  Akira Kanuma

IPC分类号： G06F9/46 ,  G06F13/24 ,  G06F13/40

CPC分类号： G06F9/462

摘要： A processor includes a bank-structured memory and is capable of handling multiple interrupts. The processor includes a central processing unit (CPU) comprising a plurality of data memories serving as general-purpose registers, and a plurality of bank specifying registers for use in specifying an address to save and restore data without involving an external system bus which connects the CPU and a program memory, such as a built-in read only memory (ROM), for storing a user program. The processor further includes a bank structured memory, connected to the CPU via an exclusive-use data bus, for holding data stored in the data memories using the bank specifying registers and for returning data stored in the bank structural memory to the data memories using the bank specifying registers. The bank specifying registers include a current bank pointer (CBP) or register for indicating a position of a bank presently in use, and a previous bank pointer (PBP) or register for indicating a bank position of data to be returned to the data memories after completing an interrupt routine. The processor may also include a program counter (PC) for indicating an address of a next instruction to be executed by the processor, a processor status word (PSW) for indicating a status of the processor, and a user stack pointer (USP) for indicating an address of a bank storing values of the program counter.

摘要翻译： 处理器包括银行结构的存储器并且能够处理多个中断。 该处理器包括一个中央处理单元（CPU），包括用作通用寄存器的多个数据存储器，以及多个存储体指定寄存器，用于指定地址以保存和恢复数据，而不涉及连接外部系统总线的外部系统总线 CPU和诸如内置只读存储器（ROM）的程序存储器，用于存储用户程序。 处理器还包括银行结构化存储器，其通过专用数据总线连接到CPU，用于使用存储体指定寄存器保存存储在数据存储器中的数据，并使用存储体结构存储器将存储在存储体结构存储器中的数据返回给数据存储器 银行指定寄存器。 存储体指定寄存器包括用于指示当前正在使用的存储体的位置的当前存储体指针（CBP）或寄存器，以及用于指示要返回数据存储器的数据的存储单元位置的先前存储体指针（PBP）或寄存器， 完成一个中断程序。 处理器还可以包括用于指示要由处理器执行的下一条指令的地址的程序计数器（PC），用于指示处理器的状态的处理器状态字（PSW）以及用于指示处理器的状态的用户堆栈指针（USP） 指示存储程序计数器的值的存储体的地址。

公开(公告)号：US20080182516A1

公开(公告)日：2008-07-31

申请号：US12019233

申请日：2008-01-24

申请人： Yasuo Yamada

发明人： Yasuo Yamada

IPC分类号： H04B7/00

CPC分类号： H04M1/2535 ,  H04M1/2745 ,  H04M1/6066 ,  H04M1/7258

摘要： According to one embodiment, an information processing apparatus, includes a changing unit which, if a command transmitted from a short-distance wireless communications terminal by pushing down a volume control button is received in a standby status in which the short-distance wireless communications terminal makes no connection with the Internet Protocol telephone communications network, changes selection of the telephone number stored in a memory unit, and a calling unit which, if a command transmitted from the short-distance wireless communications terminal by pushing down a call button is received after the changing process of the changing unit, calls the selected telephone number.

摘要翻译： 根据一个实施例，一种信息处理设备包括：改变单元，如果在短距离无线通信终端的待机状态中接收到从短距离无线通信终端通过按下音量控制按钮发送的命令， 与互联网协议电话通信网络不连接，改变存储在存储器单元中的电话号码的选择，以及呼叫单元，如果通过按下呼叫按钮从短距离无线通信终端发送的命令被接收到 更改单元的更改过程调用所选电话号码。

公开(公告)号：US07176913B2

公开(公告)日：2007-02-13

申请号：US11122006

申请日：2005-05-05

申请人： Yasuo Yamada ,  Masanori Yamaguchi

发明人： Yasuo Yamada ,  Masanori Yamaguchi

IPC分类号： G09G5/00 ,  H03M1/66

CPC分类号： G09G3/20 ,  G09G3/3208 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0297 ,  G09G2320/0276

摘要： A drive circuit for a flat display apparatus is disclosed wherein different display objects can be displayed at a time individually with appropriate gamma characteristics. Reference voltages are produced in a plurality of systems having different gamma characteristics from each other, and one of the systems is selected in response to a selection signal. Then, the reference voltages of the selected system are selected in response to image data to set gradations of pixels.

摘要翻译： 公开了一种用于平面显示装置的驱动电路，其中可以一次显示不同的显示对象，具有适当的伽马特性。 在具有彼此具有不同伽马特性的多个系统中产生参考电压，并且响应于选择信号选择系统中的一个。 然后，响应于图像数据选择所选系统的参考电压以设置像素的等级。

公开(公告)号：US20060068132A1

公开(公告)日：2006-03-30

申请号：US11221699

申请日：2005-09-09

申请人： Takuya Nakao ,  Yasuo Yamada

发明人： Takuya Nakao ,  Yasuo Yamada

IPC分类号： B41M5/00

CPC分类号： B41M5/5218 ,  G03F7/2018

摘要： To provide an ink jet recording sheet for plate-making mask film, which has good exposure characteristics and which presents good air release when contacted with a photosensitive resin plate under reduced pressure. An ink jet recording sheet for plate-making mask film, which comprises a substrate sheet and a porous layer formed thereon and has a total luminous transmittance of at least 70% as stipulated by JIS-K7361-1, wherein the porous layer comprises 100 parts by mass of inorganic particles selected from the group consisting of alumina, alumina hydrate, silica and a silica-alumina composite and having an average particle size of at most 250 nm, from 1 to 30 parts by mass of a binder and from 0.1 to 3 parts by mass of porous particles having an average particle size of from 4 to 15 μm and has a thickness of from 5 to 50 μm and an Oken type smoothness of from 200 to 10,000 seconds as stipulated by J. TAPPI No. 5-2.

摘要翻译： 提供一种制版掩模薄膜用喷墨记录纸，其具有良好的曝光特性，并且在与感光树脂板在减压下接触时具有良好的空气释放性。 一种用于制版掩模膜的喷墨记录纸，其包括基板和形成在其上的多孔层，并且其总透光率至少为JIS-K7361-1规定的70％，其中多孔层包括100份 的由氧化铝，水合氧化铝，二氧化硅和二氧化硅 - 氧化铝复合体构成的组的无机粒子，平均粒径为250nm以下，1〜30质量份的粘合剂和0.1〜3质量％ 按照J.TAPPI No.5-2的规定，平均粒径为4〜15μm，厚度为5〜50μm，Oken型平滑度为200〜10,000秒的多孔质量份。

公开(公告)号：US20050253831A1

公开(公告)日：2005-11-17

申请号：US11122006

申请日：2005-05-05

申请人： Yasuo Yamada ,  Masanori Yamaguchi

发明人： Yasuo Yamada ,  Masanori Yamaguchi

IPC分类号： H01L51/50 ,  G09G3/20 ,  G09G3/30 ,  G09G3/36 ,  H04N5/66 ,  H04N5/70 ,  H05B33/14

CPC分类号： G09G3/20 ,  G09G3/3208 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0297 ,  G09G2320/0276

摘要： A drive circuit for a flat display apparatus is disclosed wherein different display objects can be displayed at a time individually with appropriate gamma characteristics. Reference voltages are produced in a plurality of systems having different gamma characteristics from each other, and one of the systems is selected in response to a selection signal. Then, the reference voltages of the selected system are selected in response to image data to set gradations of pixels.

摘要翻译： 公开了一种用于平面显示装置的驱动电路，其中可以一次显示不同的显示对象，具有适当的伽马特性。 在具有彼此具有不同伽马特性的多个系统中产生参考电压，并且响应于选择信号选择系统中的一个。 然后，响应于图像数据选择所选系统的参考电压以设置像素的等级。

公开(公告)号：US06590475B2

公开(公告)日：2003-07-08

申请号：US09838391

申请日：2001-04-19

申请人： Yasuo Yamada ,  Kikuo Tsunoda ,  Masayuki Atokawa ,  Hirofumi Miyamoto ,  Hajime Suemasa

发明人： Yasuo Yamada ,  Kikuo Tsunoda ,  Masayuki Atokawa ,  Hirofumi Miyamoto ,  Hajime Suemasa

IPC分类号： H01P1202

CPC分类号： H01P1/2136 ,  H03H7/0123 ,  H03H7/463 ,  H04B1/52

摘要： A filter with which it is possible to control the relationship between a pass band and an attenuation band. In this filter, for example, a single-stage trap filter is electrically connected to a three-stage band pass filter via a coupling capacitor. The trap filter has a serial resonance section composed of a resonator and a resonance capacitor. The serial resonance section is connected in parallel to a capacitive reactance element (capacitor), and a serial circuit composed of an inductive reactance element (inductor) and a PIN diode as a switching element. The capacitive reactance element and the inductive reactance element both serve to make an admittance of the trap circuit substantially zero.