公开(公告)号：US20120320686A1

公开(公告)日：2012-12-20

申请号：US13593046

申请日：2012-08-23

申请人： Yasushi Takahashi ,  Toru Ishikawa

发明人： Yasushi Takahashi ,  Toru Ishikawa

IPC分类号： G11C7/10

CPC分类号： G11C11/4096 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

摘要： A system including a controller and a memory chip. The controller includes first and second selection signal terminals supplying first and second selection signals, respectively, multiple first data terminals and multiple second data terminals. The memory chip includes a semiconductor substrate, third and fourth selection signal terminals provided on the semiconductor substrate and electrically coupled to the first and second selection signal terminals of the controller, respectively. Multiple third data terminals are provided on the semiconductor substrate and electrically coupled to the first data terminals of the controller, respectively. Multiple fourth data terminals are provided on the semiconductor substrate and electrically coupled to the second data terminals of the controller, respectively. The first and third data terminals communicate first data in response to the first selection signal. The second and fourth data terminals communicate second data in response to the second selection signal.

摘要翻译： 一种包括控制器和存储器芯片的系统。 控制器包括分别提供第一和第二选择信号的第一和第二选择信号端，多个第一数据终端和多个第二数据终端。 存储器芯片包括半导体衬底，设置在半导体衬底上并分别电耦合到控制器的第一和第二选择信号端子的第三和第四选择信号端子。 多个第三数据端子分别设置在半导体衬底上并电连接到控制器的第一数据端。 多个第四数据端子分别设置在半导体衬底上并电连接到控制器的第二数据端。 第一和第三数据终端响应于第一选择信号来传送第一数据。 第二和第四数据终端响应于第二选择信号传送第二数据。

公开(公告)号：US08654557B2

公开(公告)日：2014-02-18

申请号：US13593046

申请日：2012-08-23

申请人： Yasushi Takahashi ,  Toru Ishikawa

发明人： Yasushi Takahashi ,  Toru Ishikawa

IPC分类号： G11C5/06

CPC分类号： G11C11/4096 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

摘要： A system including a controller and a memory chip. The controller includes first and second selection signal terminals supplying first and second selection signals, respectively, multiple first data terminals and multiple second data terminals. The memory chip includes a semiconductor substrate, third and fourth selection signal terminals provided on the semiconductor substrate and electrically coupled to the first and second selection signal terminals of the controller, respectively. Multiple third data terminals are provided on the semiconductor substrate and electrically coupled to the first data terminals of the controller, respectively. Multiple fourth data terminals are provided on the semiconductor substrate and electrically coupled to the second data terminals of the controller, respectively. The first and third data terminals communicate first data in response to the first selection signal. The second and fourth data terminals communicate second data in response to the second selection signal.

摘要翻译： 一种包括控制器和存储器芯片的系统。 控制器包括分别提供第一和第二选择信号的第一和第二选择信号端，多个第一数据终端和多个第二数据终端。 存储器芯片包括半导体衬底，设置在半导体衬底上并分别电耦合到控制器的第一和第二选择信号端子的第三和第四选择信号端子。 多个第三数据端子分别设置在半导体衬底上并电连接到控制器的第一数据端。 多个第四数据端子分别设置在半导体衬底上并电连接到控制器的第二数据端。 第一和第三数据终端响应于第一选择信号来传送第一数据。 第二和第四数据终端响应于第二选择信号传送第二数据。

公开(公告)号：US08274844B2

公开(公告)日：2012-09-25

申请号：US12784147

申请日：2010-05-20

申请人： Yasushi Takahashi ,  Toru Ishikawa

发明人： Yasushi Takahashi ,  Toru Ishikawa

IPC分类号： G11C7/00

CPC分类号： G11C11/4096 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

摘要： To include first and second data input/output terminals allocated to first and second memory circuit units, respectively, and an address terminal allocated in common to these memory circuit units. When a first chip selection signal is activated, the first memory circuit unit performs a read operation or a write operation via the first data input/output terminal based on an address signal regardless of an operation of the second memory circuit unit. When a second chip selection signal is activated, the second memory circuit unit performs a read operation or a write operation via the second data input/output terminal based on the address signal regardless of an operation of the first memory circuit unit. With this configuration, a wasteful data transfer can be prevented, and the effective data transfer rate can be increased.

摘要翻译： 分别包括分配给第一和第二存储器电路单元的第一和第二数据输入/输出端子以及共同分配给这些存储器电路单元的地址端子。 当第一芯片选择信号被激活时，与第二存储器电路单元的操作无关地，第一存储器电路单元基于地址信号经由第一数据输入/输出端执行读操作或写操作。 当第二芯片选择信号被激活时，第二存储器电路单元基于地址信号执行经由第二数据输入/输出端子的读取操作或写入操作，而与第一存储器电路单元的操作无关。 利用这种配置，可以防止浪费的数据传送，并且可以提高有效的数据传送速率。

公开(公告)号：US20140126300A1

公开(公告)日：2014-05-08

申请号：US14155993

申请日：2014-01-15

申请人： Yasushi Takahashi ,  Toru Ishikawa

发明人： Yasushi Takahashi ,  Toru Ishikawa

IPC分类号： G11C11/4096 ,  G11C11/4093

CPC分类号： G11C11/4096 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

摘要： To include first and second data input/output terminals allocated to first and second memory circuit units, respectively, and an address terminal allocated in common to these memory circuit units. When a first chip selection signal is activated, the first memory circuit unit performs a read operation or a write operation via the first data input/output terminal based on an address signal regardless of an operation of the second memory circuit unit. When a second chip selection signal is activated, the second memory circuit unit performs a read operation or a write operation via the second data input/output terminal based on the address signal regardless of an operation of the first memory circuit unit. With this configuration, a wasteful data transfer can be prevented, and the effective data transfer rate can be increased.

摘要翻译： 分别包括分配给第一和第二存储器电路单元的第一和第二数据输入/输出端子以及共同分配给这些存储器电路单元的地址端子。 当第一芯片选择信号被激活时，与第二存储器电路单元的操作无关地，第一存储器电路单元基于地址信号经由第一数据输入/输出端执行读操作或写操作。 当第二芯片选择信号被激活时，第二存储器电路单元基于地址信号执行经由第二数据输入/输出端子的读取操作或写入操作，而与第一存储器电路单元的操作无关。 利用这种配置，可以防止浪费的数据传送，并且可以提高有效的数据传送速率。

公开(公告)号：US08605518B2

公开(公告)日：2013-12-10

申请号：US13593018

申请日：2012-08-23

申请人： Yasushi Takahashi ,  Toru Ishikawa

发明人： Yasushi Takahashi ,  Toru Ishikawa

IPC分类号： G11C7/00

CPC分类号： G11C11/4096 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

摘要： A semiconductor device that includes a semiconductor substrate. First and second mode registers are provided on the semiconductor substrate and store information, respectively. First and second circuits are provided on the semiconductor substrate. The first and second circuits have substantially the same configuration. The first and second circuits perform an operation in response to the information of the first and second mode registers, respectively.

摘要翻译： 一种半导体器件，包括半导体衬底。 分别在半导体基板上提供第一和第二模式寄存器并存储信息。 第一和第二电路设置在半导体衬底上。 第一和第二电路具有基本上相同的构造。 第一和第二电路分别响应于第一和第二模式寄存器的信息执行操作。

公开(公告)号：US20100302874A1

公开(公告)日：2010-12-02

申请号：US12784147

申请日：2010-05-20

申请人： Yasushi Takahashi ,  Toru Ishikawa

发明人： Yasushi Takahashi ,  Toru Ishikawa

IPC分类号： G11C7/10 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C11/4096 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

摘要： To include first and second data input/output terminals allocated to first and second memory circuit units, respectively, and an address terminal allocated in common to these memory circuit units. When a first chip selection signal is activated, the first memory circuit unit performs a read operation or a write operation via the first data input/output terminal based on an address signal regardless of an operation of the second memory circuit unit. When a second chip selection signal is activated, the second memory circuit unit performs a read operation or a write operation via the second data input/output terminal based on the address signal regardless of an operation of the first memory circuit unit. With this configuration, a wasteful data transfer can be prevented, and the effective data transfer rate can be increased.

摘要翻译： 分别包括分配给第一和第二存储器电路单元的第一和第二数据输入/输出端子以及共同分配给这些存储器电路单元的地址端子。 当第一芯片选择信号被激活时，与第二存储器电路单元的操作无关地，第一存储器电路单元基于地址信号经由第一数据输入/输出端执行读操作或写操作。 当第二芯片选择信号被激活时，第二存储器电路单元基于地址信号执行经由第二数据输入/输出端子的读取操作或写入操作，而与第一存储器电路单元的操作无关。 利用这种配置，可以防止浪费的数据传送，并且可以提高有效的数据传送速率。

公开(公告)号：US08068379B1

公开(公告)日：2011-11-29

申请号：US09050946

申请日：1998-03-31

申请人： Tsutomu Takahashi ,  Kouji Arai ,  Yasushi Takahashi ,  Atsuya Tanaka ,  Shunichi Sukegawa ,  Shinji Bessho ,  Masayuki Hira

发明人： Tsutomu Takahashi ,  Kouji Arai ,  Yasushi Takahashi ,  Atsuya Tanaka ,  Shunichi Sukegawa ,  Shinji Bessho ,  Masayuki Hira

IPC分类号： G11C8/00

CPC分类号： H01L27/0207 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4097 ,  H01L27/10891

摘要： A plurality of sub word lines each have a length equivalent to the division of a main word line along the extension direction thereof, arranged along a bit line crossing said main word line, and are connected with a plurality of memory cells. A first sub word select line arranged in parallel to the main word line is extended to a plurality of sub arrays arranged in the extension direction of the word line. A second sub word select line is connected to the corresponding one of said first sub word select line to be extended orthogonally to a word line driving circuit area of an adjacent sub array. In the sub word line driving circuit provided for each sub array, a sub word line is selected and deselected by signals supplied from said main word line and said second sub word select line.

摘要翻译： 多个子字线各自具有与沿着其延伸方向的主字线的划分相等的长度，沿着与所述主字线交叉的位线布置，并且与多个存储单元连接。 与主字线平行布置的第一子字选择线被扩展到沿字线的延伸方向布置的多个子阵列。 第二子字选择线连接到所述第一子字选择线中的相应一个，以与正交相邻子阵列的字线驱动电路区域正交延伸。 在为每个子阵列提供的子字线驱动电路中，通过从所述主字线和所述第二子字选择线提供的信号来选择和取消副字线。

公开(公告)号：USD622368S1

公开(公告)日：2010-08-24

申请号：US29327935

申请日：2008-11-14

申请人： Yasushi Takahashi ,  Masahiro Maruhashi

设计人： Yasushi Takahashi ,  Masahiro Maruhashi

公开(公告)号：US07773305B2

公开(公告)日：2010-08-10

申请号：US12302849

申请日：2008-03-25

申请人： Hayato Yoshida ,  Yasushi Takahashi ,  Naoki Moniwa ,  Toshiyuki Kawasaki ,  Ryosuke Kasahara ,  Issei Abe ,  Yukiko Hamano

发明人： Hayato Yoshida ,  Yasushi Takahashi ,  Naoki Moniwa ,  Toshiyuki Kawasaki ,  Ryosuke Kasahara ,  Issei Abe ,  Yukiko Hamano

IPC分类号： G02B3/00 ,  G02B9/00 ,  G02B13/18 ,  G02B3/02 ,  G02B9/34

CPC分类号： G02B13/06 ,  G02B9/34

摘要： A wide-angle lens is disclosed that includes a front lens group and a rear lens group that are arranged in order from an object side to an image side with an aperture being arranged between the front lens group and the rear lens group. The front lens group includes at least two lenses arranged toward the object side that have negative powers, and at least one lens arranged toward the image side that has a positive power. The rear lens group includes at least one lens having a positive power. One of the lenses of the front lens group arranged second in order from the object side has a lens face that is arranged into an aspheric surface. The front lens group, the aperture, and the rear lens group make up an image forming system having an angle of view greater than 180 degrees.

摘要翻译： 公开了一种广角镜头，其包括从物体侧到像侧依次布置的前透镜组和后透镜组，其中孔被布置在前透镜组和后透镜组之间。 前透镜组包括朝向物体侧布置的具有负功率的至少两个透镜，以及朝向具有正光焦度的图像侧布置的至少一个透镜。 后透镜组包括至少一个具有正功率的透镜。 从物体侧依次排列的前透镜组的透镜中的一个具有布置在非球面中的透镜面。 前透镜组，光圈和后透镜组构成具有大于180度的视角的图像形成系统。

公开(公告)号：US20090243823A1

公开(公告)日：2009-10-01

申请号：US12382826

申请日：2009-03-24

申请人： Yasushi Takahashi

发明人： Yasushi Takahashi

IPC分类号： B60Q1/00 ,  H04N13/02 ,  G06K9/00

CPC分类号： G06K9/00805 ,  H04N13/239 ,  H04N13/246

摘要： A vehicle environment recognition apparatus includes stereo-image taking means for outputting a reference image of the surroundings of a subject vehicle, stereo matching means for correlating a parallax with each pixel block in the reference image by stereo matching, preceding-vehicle detecting means for detecting a preceding vehicle from the reference image on the basis of the parallax or the like, and smear determining means for searching a pixel column vertically extending in the reference image for brightnesses of pixels, the pixel column including a pixel block having a parallax less than or equal to a long-distance parallax threshold value corresponding to the long distance including infinity, and determining that a smear occurs when a ratio of the number of pixels having brightnesses more than or equal to a predetermined brightness to the total number of pixels in the pixel column is more than or equal to a predetermined ratio.

摘要翻译： 车辆环境识别装置包括立体图像摄取装置，用于输出本车辆的周围环境的参考图像，用于通过立体匹配将视差与参考图像中的每个像素块相关联的立体匹配装置，用于检测的前车检测装置 基于视差等的参考图像的前车，以及用于搜索在参考图像中垂直延伸的像素列用于像素亮度的拖尾确定装置，该像素列包括具有小于或等于视差的视差的像素块， 等于与包括无穷远的长距离相对应的长距离视差阈值，并且当具有大于或等于预定亮度的亮度的像素的数量与像素中的像素总数的比率时，确定拖尾发生 列大于或等于预定比例。