公开(公告)号：US06424052B1

公开(公告)日：2002-07-23

申请号：US09154250

申请日：1998-09-16

申请人： Yasuyuki Miyamoto ,  Hiroo Hongo

发明人： Yasuyuki Miyamoto ,  Hiroo Hongo

IPC分类号： H01L23544

CPC分类号： H01J37/3045 ,  H01J2237/30438 ,  H01J2237/3175 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： An alignment mark for use in electron beam lithography for manufacturing a fine semiconductor structure by repeating a regrowth of a compound semiconductor layer and a fine process including electron beam exposure. The alignment mark includes a lower protection layer made of tungsten formed on a compound semiconductor substrate, a mark main body made of gold, chromium or platinum shaped into a desired pattern having a sharp edge profile which generates a detection signal of a mark position having a large gain, and an upper protection layer covering the mark main body and made of silicon oxide which does not react significantly with substances constituting a compound semiconductor layer. The mark main body has a thickness which is not less than 100 nm.

摘要翻译： 用于电子束光刻的对准标记，用于通过重复化合物半导体层的再生长和包括电子束曝光的精细工艺来制造精细的半导体结构。 对准标记包括形成在化合物半导体衬底上的由钨制成的下保护层，由金，铬或铂制成的具有尖锐边缘轮廓的所需图案的标记主体，其形成具有尖锐边缘轮廓的标记位置的检测信号， 大的增益和覆盖标记主体并由与构成化合物半导体层的物质不显着反应的氧化硅制成的上保护层。 标记主体的厚度不小于100nm。

公开(公告)号：US5625206A

公开(公告)日：1997-04-29

申请号：US657255

申请日：1996-06-03

申请人： S. Chandrasekhar ,  Andrew G. Dentai ,  Yasuyuki Miyamoto

发明人： S. Chandrasekhar ,  Andrew G. Dentai ,  Yasuyuki Miyamoto

IPC分类号： H01L29/737 ,  H01L29/201

CPC分类号： H01L29/7371

摘要： The total base-collector capacitance of a double-heterostructure bipolar transistor device is reduced by removing semiconductor material from the extrinsic regions and replacing the removed material with a relatively-low-dielectric-constant material, The base-collector capacitance is further reduced by using a composite subcollector structure that permits the extrinsic regions to be made thicker than the intrinsic region of the device.

摘要翻译： 通过从外部区域去除半导体材料并用相对低介电常数的材料代替去除的材料，可以减少双异质结双极晶体管器件的总基极 - 集电极电容。基极 - 集电极电容通过使用 复合子集电极结构，其允许外部区域被制成比该器件的本征区域更厚。

公开(公告)号：US5656515A

公开(公告)日：1997-08-12

申请号：US683291

申请日：1996-07-18

申请人： S. Chandrasekhar ,  Andrew Gomperz Dentai ,  Yasuyuki Miyamoto

发明人： S. Chandrasekhar ,  Andrew Gomperz Dentai ,  Yasuyuki Miyamoto

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/205 ,  H01L29/737 ,  H01L21/265

CPC分类号： H01L29/66318 ,  H01L29/7371 ,  Y10S438/97

摘要： The lateral base resistance of a DHBT device is reduced and its high-speed operating characteristics thereby improved by forming a structure that initially includes a relatively thick extrinsic base layer overlying a relatively thin intrinsic base layer. The extrinsic base layer is then etched to form a window in which an emitter layer is deposited. In that way, the growth time for formation of the base-emitter junction is minimized. High-performance devices are thereby realized in a relatively simple process that has advantageous self-alignment features.

摘要翻译： DHBT器件的横向基极电阻降低，并且其高速工作特性因此通过形成最初包括覆盖相对较薄的本征基极层的较厚外部基极层的结构而得以改善。 然后蚀刻非本征基层以形成其中沉积发射极层的窗口。 以这种方式，形成基极 - 发射极结的生长时间被最小化。 因此，在具有有利的自对准特征的相对简单的过程中实现高性能装置。

公开(公告)号：US5436096A

公开(公告)日：1995-07-25

申请号：US963695

申请日：1992-10-20

申请人： Kazuhito Furuya ,  Yasuyuki Miyamoto

发明人： Kazuhito Furuya ,  Yasuyuki Miyamoto

IPC分类号： G03F1/22 ,  H01L21/027 ,  G03F9/00

CPC分类号： G03F1/22

摘要： The present invention can precisely manufacture an X-ray mask pattern at intervals of less than 10 nm by using a thin film crystalline growth method, applying a laminated layer body of a fine structure having a precision of less than 1 atomic layer onto a substrate, and utilizing the difference in X-ray absorption coefficients. A method of manufacturing an X-ray exposure mask comprises the steps of alternately laminating two kinds of material consisting of a combination of a semiconductor, metal and insulator having substantially equal lattice constants and largely different coefficients of X-ray absorption on a substrate of a crystal body to thicknesses of less than 10 .ANG. by an epitaxial crystal growth method, and manufacturing a mask for exposing streak-like X-rays on a desired resist as a result of the largely different coefficients of X-ray absorption between each layer.

摘要翻译： 本发明可以通过使用薄膜晶体生长方法以小于10nm的间隔精确地制造X射线掩模图案，将具有小于1原子层的精密度的精细结构的层叠体施加到基板上， 并利用X射线吸收系数的差异。 一种制造X射线曝光掩模的方法包括以下步骤：将由半导体，金属和绝缘体的组合构成的两种材料交替层叠，所述半导体，金属和绝缘体具有基本相等的晶格常数和大体上不同的X射线吸收系数， 晶体通过外延晶体生长方法的厚度小于10，并且由于各层之间的X射线吸收系数大大不同，制造用于在期望的抗蚀剂上暴露条纹状X射线的掩模。

公开(公告)号：US5364717A

公开(公告)日：1994-11-15

申请号：US953669

申请日：1992-10-01

申请人： Kazuhito Furuya ,  Yasuyuki Miyamoto

发明人： Kazuhito Furuya ,  Yasuyuki Miyamoto

IPC分类号： G03F1/22 ,  H01L21/027 ,  G03F9/00

CPC分类号： G03F1/22

摘要： The present invention relates to a method of manufacturing an exposure mask having an unprecedented supermicrostructure for an X-ray exposure method favorable for conventional supermicro exposure using lithography techniques. The method of manufacturing an X-ray exposure mask comprises the steps of alternately laminating two kinds of compound semiconductors as a thin film having a periodic structure with controllability of about one atomic layer on a substrate selectively etching only one material for forming the periodic structure, forming an uneven difference between adjacent layers of the laminate body, and manufacturing a mask for exposing streaks on a desired resist with the aid of a difference of X-rays absorption amounts between each layer by exposing X-ray in parallel to the direction of the laminate layer.

摘要翻译： 本发明涉及一种制造曝光掩模的方法，该曝光掩模具有前所未有的超微结构，用于有利于使用光刻技术的常规超微曝光的X射线曝光方法。 制造X射线曝光掩模的方法包括以下步骤：在基板上交替层叠两种化合物半导体作为具有约一个原子层的可控性的具有周期性结构的薄膜的选择性地仅刻蚀形成周期性结构的一种材料， 在层压体的相邻层之间形成不均匀的差异，并且制造用于通过将X射线平行于每个层的方向上的X射线吸收量的差异来在所需抗蚀剂上暴露条纹的掩模 层压层。

公开(公告)号：US20090302351A1

公开(公告)日：2009-12-10

申请号：US12093950

申请日：2006-11-16

申请人： Yasuyuki Miyamoto ,  Tohru Yamamoto ,  Masashi Ishida

发明人： Yasuyuki Miyamoto ,  Tohru Yamamoto ,  Masashi Ishida

IPC分类号： H01L29/737 ,  H01L21/331

CPC分类号： H01L29/7371 ,  H01L29/66318

摘要： A bipolar transistor (1) comprising a subcollector layer (3), a collector layer (4, 5), a base layer (6) and an emitter layer (7) which are successively built up and having: the subcollector layer (3) formed with a projection (3A) and recesses (3B), an upper part above the projection constituting an intrinsic transistor region (1A) of the bipolar transistor; insulator layer (10) buried between the recesses of the subcollector layer and the collector layer (4); a boundary interface between the subcollector layer and the collector layer held between the insulator layers; the base layer (6) made of a single crystal layer and provided with a base electrode (12) on a region becoming an extrinsic base layer (6B) of the base layer; and the subcollector layer provided with a collector electrode (11). The bipolar transistor has advantages of its emitter made finer in width, a reduced parasitic capacitance between its base and collector and improved high-frequency characteristics.

摘要翻译： 一种双极晶体管（1），包括分别集电极层（3），集电极层（4,5），基极层（6）和发射极层（7），它们被连续地构建并具有：子集电极层（3） 形成有突起（3A）和凹部（3B），在突出部上方的上部构成双极晶体管的本征晶体管区域（1A）; 埋置在子集电极层的凹部和集电体层（4）之间的绝缘体层（10）; 子集电极层和保持在绝缘体层之间的集电极层之间的边界界面; 所述基底层（6）由单晶层制成，并且在成为所述基底层的外在基底层（6B）的区域上设置有基极（12） 以及设置有集电极（11）的子集电极层。 双极晶体管的优点在于其发射极宽度较窄，其基极和集电极之间的寄生电容降低，并提高了高频特性。

公开(公告)号：US07923754B2

公开(公告)日：2011-04-12

申请号：US12093950

申请日：2006-11-16

申请人： Yasuyuki Miyamoto ,  Tohru Yamamoto ,  Masashi Ishida

发明人： Yasuyuki Miyamoto ,  Tohru Yamamoto ,  Masashi Ishida

IPC分类号： H01L21/331

CPC分类号： H01L29/7371 ,  H01L29/66318

摘要： A bipolar transistor (1) comprising a subcollector layer (3), a collector layer (4, 5), a base layer (6) and an emitter layer (7) which are successively built up and having: the subcollector layer (3) formed with a projection (3A) and recesses (3B), an upper part above the projection constituting an intrinsic transistor region (1A) of the bipolar transistor; insulator layer (10) buried between the recesses of the subcollector layer and the collector layer (4); a boundary interface between the subcollector layer and the collector layer held between the insulator layers; the base layer (6) made of a single crystal layer and provided with a base electrode (12) on a region becoming an extrinsic base layer (6B) of the base layer; and the subcollector layer provided with a collector electrode (11). The bipolar transistor has advantages of its emitter made finer in width, a reduced parasitic capacitance between its base and collector and improved high-frequency characteristics.

摘要翻译： 一种双极晶体管（1），包括分别集电极层（3），集电极层（4,5），基极层（6）和发射极层（7），它们被连续地构建并具有：子集电极层（3） 形成有突起（3A）和凹部（3B），在突出部上方的上部构成双极晶体管的本征晶体管区域（1A）; 埋置在子集电极层的凹部和集电体层（4）之间的绝缘体层（10）; 子集电极层和保持在绝缘体层之间的集电极层之间的边界界面; 所述基底层（6）由单晶层制成，并且在成为所述基底层的外在基底层（6B）的区域上设置有基极（12） 以及设置有集电极（11）的子集电极层。 双极晶体管的优点在于其发射极宽度较窄，其基极和集电极之间的寄生电容降低，并提高了高频特性。

公开(公告)号：US06919274B2

公开(公告)日：2005-07-19

申请号：US10780670

申请日：2004-02-19

申请人： Hideyuki Kazumi ,  Tsuyoshi Yoshida ,  Eiji Ikegami ,  Kouichi Nakaune ,  Masamichi Sakaguchi ,  Yasuyuki Miyamoto ,  Akihiro Sano

发明人： Hideyuki Kazumi ,  Tsuyoshi Yoshida ,  Eiji Ikegami ,  Kouichi Nakaune ,  Masamichi Sakaguchi ,  Yasuyuki Miyamoto ,  Akihiro Sano

IPC分类号： H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/44

CPC分类号： H01L21/31116

摘要： An apparatus for performing a plasma-etching of a LSI device including a Cu interconnection, a low-k film, and a diffusion prevention film has a treatment chamber, into which an etching gas is introduced, and a support table which is equipped with electrodes and on which said LSI device is placed. In this apparatus, the etching gasses are turned into plasma by supplying radio frequency power to electrodes provided within the treatment chamber, so that the LSI device is etched with ions of the plasma. In this apparatus, a sulfur-containing gas and a fluorine-containing gas are mixed to the etching gasses, so that the diffusion prevention film is selectively etched against the low-k film.

公开(公告)号：US20050026431A1

公开(公告)日：2005-02-03

申请号：US10780670

申请日：2004-02-19

申请人： Hideyuki Kazumi ,  Tsuyoshi Yoshida ,  Eiji Ikegami ,  Kouichi Nakaune ,  Masamichi Sakaguchi ,  Yasuyuki Miyamoto ,  Akihiro Sano

发明人： Hideyuki Kazumi ,  Tsuyoshi Yoshida ,  Eiji Ikegami ,  Kouichi Nakaune ,  Masamichi Sakaguchi ,  Yasuyuki Miyamoto ,  Akihiro Sano

IPC分类号： H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/44

CPC分类号： H01L21/31116

摘要： An apparatus for performing a plasma-etching of a LSI device including a Cu interconnection, a low-k film, and a diffusion prevention film has a treatment chamber, into which an etching gas is introduced, and a support table which is equipped with electrodes and on which said LSI device is placed. In this apparatus, the etching gasses are turned into plasma by supplying radio frequency power to electrodes provided within the treatment chamber, so that the LSI device is etched with ions of the plasma. In this apparatus, a sulfur-containing gas and a fluorine-containing gas are mixed to the etching gasses, so that the diffusion prevention film is selectively etched against the low-k film.

摘要翻译： 用于进行包括Cu互连，低k膜和防扩散膜的LSI器件的等离子体蚀刻的设备具有其中引入蚀刻气体的处理室和配备有电极的支撑台 并在其上放置所述LSI器件。 在该装置中，通过向设置在处理室内的电极提供射频功率使蚀刻气体变成等离子体，从而利用等离子体的离子蚀刻LSI器件。 在该装置中，将含硫气体和含氟气体混合到蚀刻气体中，使得防扩散膜针对低k膜选择性地蚀刻。