公开(公告)号：US20050208712A1

公开(公告)日：2005-09-22

申请号：US11128010

申请日：2005-05-12

申请人： Yeen Chan ,  Kheng Tee ,  Yiang Nga ,  Zhao Lun ,  Wang Goh ,  Diing Ang

发明人： Yeen Chan ,  Kheng Tee ,  Yiang Nga ,  Zhao Lun ,  Wang Goh ,  Diing Ang

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/00 ,  H01L21/84

CPC分类号： H01L29/66772 ,  H01L29/78615

摘要： A MOSFET device structure formed on a silicon on insulator layer, and a process sequence employed to fabricate said MOSFET device structure, has been developed. The process features insulator filled, shallow trench isolation (STI) regions formed in specific locations of the MOSFET device structure for purposes of reducing the risk of parasitic transistor formation underlying a gate structure junction. After formation of either a “T” shaped, or an “H” shaped gate structure, body contact regions of a first conductivity type are formed adjacent to both an STI region and to a component of the gate structure. Formation of a source/drain region of a second conductivity type located on the opposite side of the same STI region, and the same gate structure component, is next performed. Unwanted parasitic transistor formation, which can occur underlying the gate structure via the body contact region and the source/drain region, is prevented by the presence of the separating STI region.

公开(公告)号：US20050023608A1

公开(公告)日：2005-02-03

申请号：US10628913

申请日：2003-07-29

申请人： Yeen Chan ,  Kheng Tee ,  Yiang Nga ,  Zhao Lun ,  Wang Goh ,  Diing Ang

发明人： Yeen Chan ,  Kheng Tee ,  Yiang Nga ,  Zhao Lun ,  Wang Goh ,  Diing Ang

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/84 ,  H01L27/12

CPC分类号： H01L29/66772 ,  H01L29/78615

摘要： A MOSFET device structure formed on a silicon on insulator layer, and a process sequence employed to fabricate said MOSFET device structure, has been developed. The process features insulator filled, shallow trench isolation (STI) regions formed in specific locations of the MOSFET device structure for purposes of reducing the risk of parasitic transistor formation underlying a gate structure junction. After formation of either a “T” shaped, or an “H” shaped gate structure, body contact regions of a first conductivity type are formed adjacent to both an STI region and to a component of the gate structure. Formation of a source/drain region of a second conductivity type located on the opposite side of the same STI region, and the same gate structure component, is next performed. Unwanted parasitic transistor formation, which can occur underlying the gate structure via the body contact region and the source/drain region, is prevented by the presence of the separating STI region.

公开(公告)号：US20050057335A1

公开(公告)日：2005-03-17

申请号：US10962007

申请日：2004-10-08

申请人： Choon-Beng Sia ,  Kiat Yeo ,  Shao-fu Chu ,  Cheng Ng ,  Kok Chew ,  Wang Goh

发明人： Choon-Beng Sia ,  Kiat Yeo ,  Shao-fu Chu ,  Cheng Ng ,  Kok Chew ,  Wang Goh

IPC分类号： H01F41/04 ,  H01F17/00 ,  H01L21/02 ,  H01L27/08 ,  H01F27/02

CPC分类号： H01L28/10 ,  H01L27/08 ,  Y10T29/4902 ,  Y10T29/4906 ,  Y10T29/49073 ,  Y10T29/49165

摘要： A method of manufacturing a 3-D spiral stacked inductor is provided having a substrate with a plurality of turns in a plurality of levels wherein the number of levels increases from an inner turn to the outer turn of the inductor. First and second connecting portions are respectively connected to an inner turn and an outermost turn, and a dielectric material contains the first and second connecting portions and the plurality of turns over the substrate.

摘要翻译： 提供了一种制造3-D螺旋堆叠电感器的方法，其具有多个电平的多个匝数的基板，其中电平的数量从电感器的内部匝数增加到外部匝数。 第一连接部分和第二连接部分分别连接到内匝和最外匝，电介质材料包含基片上的第一和第二连接部分和多个匝。

公开(公告)号：US20070075371A1

公开(公告)日：2007-04-05

申请号：US11466018

申请日：2006-08-21

申请人： Yeow Lim ,  Randall Cha ,  Alex See ,  Wang Goh

发明人： Yeow Lim ,  Randall Cha ,  Alex See ,  Wang Goh

IPC分类号： H01L23/62

CPC分类号： H01L21/76897 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.

摘要翻译： 提供一种集成电路，其具有形成在其上的第一电介质层的基极。 在第一电介质层上形成第二电介质层。 第三电介质层形成在第二电介质层上的间隔开的条带中。 第一沟槽开口通过第三和第二电介质层形成在第三介电层间隔开的条之间。 第二沟槽开口与通过第一介电层的第一沟槽开口连续地形成在第三介电层的间隔开的条之间。 沟槽开口中的导体金属形成自对准沟槽互连。