公开(公告)号：US07692440B2

公开(公告)日：2010-04-06

申请号：US10533236

申请日：2003-08-29

Applicant: Jimmy Hwee Seng Chew ,  Kok Yeow Lim ,  Fulin Liu

Inventor： Jimmy Hwee Seng Chew ,  Kok Yeow Lim ,  Fulin Liu

IPC: G01R31/26 ,  B26D7/06 ,  B24C3/32

CPC classification number: B26D5/007 ,  B24C1/045 ,  B24C3/083 ,  B26D7/06 ,  B26F3/004 ,  B26F3/008 ,  Y10T83/6604

Abstract: A water jet handler (200) has a loading location (205), a cutting location (210), and an unloading location (215); and two movable mounts (240 and a 245). As a first movable mount (240) receives a molded substrate at the loading location (205), and transports it to the cutting location (210), a second movable mount (245) transports singulated semiconductor packages of a previously singulated molded substrate from the cutting location (210) to the unloading location (215). As the molded substrate on the first movable mount (240) is cut in the X direction (232) by a water jet, the singulated semiconductor packages are unloaded. The molded substrate is then transferred to the second movable mount (245) on which it is cut in the Y direction (272) to produce singulated semiconductor packages, as the first movable mount (240) returns to the loading location (205), when another molded substrate is loaded.

Abstract translation: 喷水处理器（200）具有装载位置（205），切割位置（210）和卸载位置（215）; 和两个可移动的安装件（240和245）。 作为第一可移动安装座（240）在装载位置（205）处接收模制基板，并将其传送到切割位置（210），第二可移动安装件（245）将先前分割成型的基板的单个半导体封装从 切割位置（210）到卸载位置（215）。 当第一可移动支架（240）上的模制基板通过水射流在X方向（232）上被切割时，单片半导体封装被卸载。 然后，随着第一可移动支架（240）返回到装载位置（205），模制基板被转移到在Y方向（272）上被切割的第二可移动支架（245）以产生单个半导体封装，当 另外一个模塑基底被加载。

公开(公告)号：US20080299098A1

公开(公告)日：2008-12-04

申请号：US12109159

申请日：2008-04-24

Applicant: Chea-Yun Se ,  Fui-Fong Yong ,  Hai-Meng Tan ,  Wee Ming Yeo ,  Alex Yeow-Lim Teo

Inventor： Chea-Yun Se ,  Fui-Fong Yong ,  Hai-Meng Tan ,  Wee Ming Yeo ,  Alex Yeow-Lim Teo

IPC: A61K35/74 ,  C12N1/20 ,  A61P31/04

CPC classification number: C12R1/225 ,  A23K10/18 ,  A23L33/135 ,  A61K35/747 ,  A61L2/00 ,  C12N1/20 ,  Y02A50/47 ,  Y02A50/471 ,  Y02A50/473 ,  Y02A50/475

Abstract: The present invention demonstrated the potential use of Lactobacillus johnsonii D115 as a probiotic, as a prophylactic agent or as a surface treatment of materials against human and animal pathogens such as Brachyspira pilosicoli, Brachyspira hyodysenteriae, Shigella sonnei, Vibrio cholera, Vibrio parahaemolyticus, Campylobacter jejuni, Streptococcus pneumoniae, Enterococcus faecalis, Enterococcus faecium, Clostridium perfringens, Yersinia enterocolitica, Escherichia coli, Klebbsiella pneumoniae, Staphylococcus aureus, Salmonella spp., Bacillus cereus, Aspergillus niger and Fusarium chlamydosporum. The proteineous antimicrobial compound was partially characterized and found to be heat tolerant up to 121° C. for 15 min, and acid tolerant up to pH1 for 30 min at 40° C. The compound is also stable to enzymatic digestion, being able to retain more than 60% antimicrobial activity when treated with pepsin and trypsin.

Abstract translation: 本发明证明了约翰逊乳杆菌D115作为益生菌作为预防剂或作为对人和动物病原体的材料的表面处理的潜在用途，例如Br​​achyspira pilosicoli，猪痢疾短螺杆菌，志贺氏菌，霍乱弧菌，副溶血弧弧菌，空肠弯曲杆菌 ，肺炎链球菌，粪肠球菌，屎肠球菌，产气荚膜梭菌，小肠结肠炎耶尔森菌，大肠杆菌，肺炎克雷伯菌，金黄色葡萄球菌，沙门氏菌，蜡状芽孢杆菌，黑曲霉和衣原体枯萎病。 蛋白质抗微生物化合物被部分表征，发现耐受温度高达121℃，持续15分钟，并且在40℃下耐酸至pH1达30分钟。该化合物对酶消化也是稳定的，能够保留 用胃蛋白酶和胰蛋白酶处理时，超过60％的抗菌活性。

公开(公告)号：US07247299B2

公开(公告)日：2007-07-24

申请号：US10306365

申请日：2002-11-27

Applicant: Angeline Seah Huay Lin ,  Alex Yeow-Lim Teo ,  Tan Hai Meng

Inventor： Angeline Seah Huay Lin ,  Alex Yeow-Lim Teo ,  Tan Hai Meng

IPC: A01N63/00

CPC classification number: A61K35/742 ,  A61K38/00 ,  C07K14/32 ,  Y02A50/47

Abstract: Antimicrobial compounds from Bacillus subtilis for use against animal and human pathogens. A novel strain of Bacillus subtilis was isolated from the gastrointestinal tract of poultry and was found to produce a factor or factors that have excellent inhibitory effects on Clostridium perfringens, Clostridium difficile, Campylobacter jejuni, Campylobacter coli, and Streptococcus pneumoniae. The factor(s) retain full viability and antimicrobial activity after heat treatment. The invention provides a method of treatment of pathogenic microorganisms including C. perfringens.

Abstract translation: 用于抗动物和人类病原体的来自枯草芽孢杆菌的抗微生物化合物。 从家禽的胃肠道中分离出一株新的枯草芽孢杆菌菌株，发现产生对产气荚膜梭菌，艰难梭菌，空肠弯曲杆菌，肠杆菌和肺炎链球菌有极好抑制作用的因子。 因子在热处理后保持完整的活力和抗菌活性。 本发明提供了一种治疗包括产气荚膜梭菌在内的病原微生物的方法。

公开(公告)号：US20070075371A1

公开(公告)日：2007-04-05

申请号：US11466018

申请日：2006-08-21

Applicant: Yeow Lim ,  Randall Cha ,  Alex See ,  Wang Goh

Inventor： Yeow Lim ,  Randall Cha ,  Alex See ,  Wang Goh

IPC: H01L23/62

CPC classification number: H01L21/76897 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.

Abstract translation: 提供一种集成电路，其具有形成在其上的第一电介质层的基极。 在第一电介质层上形成第二电介质层。 第三电介质层形成在第二电介质层上的间隔开的条带中。 第一沟槽开口通过第三和第二电介质层形成在第三介电层间隔开的条之间。 第二沟槽开口与通过第一介电层的第一沟槽开口连续地形成在第三介电层的间隔开的条之间。 沟槽开口中的导体金属形成自对准沟槽互连。

公开(公告)号：US20060094339A1

公开(公告)日：2006-05-04

申请号：US10533236

申请日：2003-08-29

Applicant: Jimmy Hwee Chew ,  Kok Yeow Lim ,  Fulin Liu

Inventor： Jimmy Hwee Chew ,  Kok Yeow Lim ,  Fulin Liu

IPC: B24C1/00 ,  B24C3/32

CPC classification number: B26D5/007 ,  B24C1/045 ,  B24C3/083 ,  B26D7/06 ,  B26F3/004 ,  B26F3/008 ,  Y10T83/6604

Abstract: A water jet handler (200) has a loading location (205), a cutting location (210), and an unloading location (215); and two movable mounts (240 and a 245). As a first movable mount (240) receives a molded substrate at the loading location (205), and transport it to the cutting location (210), a second movable mount (245) transports singulated semiconductor packages of a previously singulated molded substrate from the cutting location (210) to the unloading location (215). As the molded substrate on the first movable mount (240) is cut in the X direction (232) by a water jet, the singulated semiconductor packages are unloaded. The molded substrate is then transferred to the second movable mount (245) on which it is cut in the Y direction (272) to produce singulated semiconductor packages, as the first movable mount (240) returns to the loading location (205), when another molded substrate is loaded.

Abstract translation: 喷水处理器（200）具有装载位置（205），切割位置（210）和卸载位置（215）; 和两个可移动的安装件（240和245）。 作为第一可移动安装座（240）在装载位置（205）处接收模制基板，并将其传送到切割位置（210），第二可移动安装件（245）将先前分割成型的基板的单个半导体封装从 切割位置（210）到卸载位置（215）。 当第一可移动支架（240）上的模制基板通过水射流在X方向（232）上被切割时，单片半导体封装被卸载。 然后，随着第一可移动支架（240）返回到装载位置（205），模制基板被转移到在Y方向（272）上被切割的第二可移动支架（245）以产生单个半导体封装，当 另外一个模塑基底被加载。

公开(公告)号：US20050090095A1

公开(公告)日：2005-04-28

申请号：US10690998

申请日：2003-10-22

Applicant: Yeow Lim ,  Wuping Liu ,  Tae Lee ,  Bei Zhang ,  Juan Tan ,  Alan Cuthbertson ,  Chin Neo

Inventor： Yeow Lim ,  Wuping Liu ,  Tae Lee ,  Bei Zhang ,  Juan Tan ,  Alan Cuthbertson ,  Chin Neo

IPC: H01L21/4763 ,  H01L21/768 ,  H01L29/06

CPC classification number: H01L21/76807 ,  H01L21/76829 ,  H01L21/76834

Abstract: A method of forming an aligned dual damascene opening, comprising including the following sequential steps. A structure having a metal structure formed thereover is provided. A layer stack is formed over the metal structure. The layer stack comprises, in ascending order: a bottom etch stop layer; a lower dielectric material layer; a middle etch stop layer; a middle dielectric material layer; and an upper dielectric layer. The upper dielectric layer is patterned to form an opening exposing a portion of the underlying middle dielectric material layer. The opening having a width. A patterned mask layer is formed over the patterned upper dielectric layer leaving exposed opposing portions of the patterned upper dielectric layer. The middle dielectric material layer is patterned to form an opening therein using the patterned mask layer and the exposed portions of the upper dielectric layer as masks. The middle dielectric material layer opening exposing a portion of the middle etch stop layer. The middle etch stop layer is removed at its exposed portion to form a patterned middle etch stop layer having an opening exposing a portion of the lower dielectric material layer. Simultaneously patterning: the patterned middle dielectric material layer using the patterned upper dielectric layer as a mask to form an inchoate upper trench opening; and the lower dielectric material layer using the patterned mask layer and the patterned middle etch stop layer as masks to form an inchoate lower via opening aligned with the inchoate upper trench opening. The inchoate lower via opening exposing a portion of the underlying bottom etch stop layer. The patterned mask layer is removed. The patterned upper dielectric material layer, the exposed portions of the patterned middle etch stop layer and the exposed portion of the bottom etch stop layer are removed to convert: the inchoate upper trench opening into a final upper trench opening; and the inchoate lower via opening into a final lower via opening to form the dual damascene opening.

公开(公告)号：US20070196979A1

公开(公告)日：2007-08-23

申请号：US11358801

申请日：2006-02-21

Applicant: Teck Tan ,  Hwee Seng Chew ,  Kok Yeow Lim ,  Abd. Razak Chichik ,  Kee Lau ,  Chuan Wong

Inventor： Teck Tan ,  Hwee Seng Chew ,  Kok Yeow Lim ,  Abd. Razak Chichik ,  Kee Lau ,  Chuan Wong

IPC: H01L21/8242

CPC classification number: H01L23/3107 ,  H01L21/4821 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/16 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18301 ,  H01L2224/81

Abstract: A method for forming semiconductor packages is disclosed. The method involves providing a support substrate and forming at least one conductive layer thereon. The method also includes coupling the at least one conductive layer to a support face of a film substrate for securing the at least one conductive layer to the support face and removing the support substrate from the at least one conductive layer. The at least one interconnector is adhered to the film substrate for forming an interposer. The method further involves bonding a integrated circuit chip to the at least one conductive layer of the interposer and disposing a compound over the support face to thereby encapsulate the integrated circuit chip and the least one conductive layer for forming an encapsulated package therefrom. Portions of the at least one conductive layer is then exposed by removing the film substrate from the encapsulated package.

Abstract translation: 公开了一种用于形成半导体封装件的方法。 该方法包括提供支撑衬底并在其上形成至少一个导电层。 该方法还包括将至少一个导电层耦合到薄膜基底的支撑面，用于将至少一个导电层固定到支撑面上，并从至少一个导电层移除支撑基底。 至少一个互连器粘附到膜基底上以形成插入件。 该方法还包括将集成电路芯片接合到插入器的至少一个导电层并且在支撑面上方布置化合物，从而封装集成电路芯片和用于形成封装封装的至少一个导电层。 然后通过从封装的包装中去除膜基材来暴露至少一个导电层的部分。

公开(公告)号：US20070111522A1

公开(公告)日：2007-05-17

申请号：US11273108

申请日：2005-11-12

Applicant: Yeow Lim ,  Wei Lu ,  Liang Hsia ,  Jyoti Gupta ,  Chim Seet ,  Hao Zhang

Inventor： Yeow Lim ,  Wei Lu ,  Liang Hsia ,  Jyoti Gupta ,  Chim Seet ,  Hao Zhang

IPC: H01L21/44

CPC classification number: H01L21/76831 ,  H01L21/2855 ,  H01L21/76849 ,  H01L21/76877

Abstract: A method of fabrication of a sputtered metal silicide layer over a copper interconnect. We form a dielectric layer over a conductive layer. We form an interconnect opening in the dielectric layer. We form a copper layer at least filling the interconnect opening. We planarize the copper layer to form a copper interconnect in the interconnect opening. The copper interconnect is over polished to form a depression. We form metal silicide layer over the copper interconnect using a low temperature sputtering process. We can form a cap layer over the metal silicide layer.

Abstract translation: 一种在铜互连上制造溅射金属硅化物层的方法。 我们在导电层上形成介电层。 我们在电介质层中形成互连开口。 我们形成至少填充互连开口的铜层。 我们平面化铜层以在互连开口中形成铜互连。 铜互连件被抛光以形成凹陷。 我们使用低温溅射工艺在铜互连上形成金属硅化物层。 我们可以在金属硅化物层上形成覆盖层。

公开(公告)号：US20060040491A1

公开(公告)日：2006-02-23

申请号：US10923123

申请日：2004-08-21

Applicant: Yeow Lim ,  Alex See ,  Tae Lee ,  David Vigar ,  Liang Hsia ,  Kin Pey

Inventor： Yeow Lim ,  Alex See ,  Tae Lee ,  David Vigar ,  Liang Hsia ,  Kin Pey

IPC: H01L21/4763

CPC classification number: H01L23/528 ,  H01L21/0276 ,  H01L21/288 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.

Abstract translation: 用于宽线槽以减少压力的方法和结构。 一种示例性实施例的方法和结构是一种互连结构，包括：包括宽线的互连。 宽线有第一个插槽。 第一槽与通孔塞隔开第一距离，使得第一槽减轻宽线和通孔塞上的应力。 通孔插头可以从上方或下方接触宽线。 另一个示例性实施例是双镶嵌互连结构，包括：双镶嵌形互连件，其包括通孔塞，第一槽和宽线。 宽线有第一个插槽。 第一槽与通孔塞隔开第一距离，使得第一槽减轻宽线和通孔塞上的应力。

公开(公告)号：US20060003573A1

公开(公告)日：2006-01-05

申请号：US11174805

申请日：2005-07-05

Applicant: Yeow Lim ,  Wuping Liu ,  Tae Lee ,  Bei Zhang ,  Juan Boon Tan ,  Alan Cuthbertson ,  Chin Neo

Inventor： Yeow Lim ,  Wuping Liu ,  Tae Lee ,  Bei Zhang ,  Juan Boon Tan ,  Alan Cuthbertson ,  Chin Neo

IPC: H01L21/4763

CPC classification number: H01L21/76807 ,  H01L21/76829 ,  H01L21/76834

Abstract: An aligned dual damascene opening structure, comprising the following. A structure having a metal structure formed thereover. A patterned layer stack over the metal structure; the layer stack comprising, in ascending order: a patterned bottom etch stop layer; a patterned lower dielectric material layer; a patterned middle etch stop layer; and a patterned middle dielectric material layer; the lower and middle dielectric layers being comprised of the same material. An upper trench opening in the patterned bottom etch stop layer and the patterned lower dielectric material layer; and a lower via opening in the patterned middle etch stop layer and the patterned middle dielectric material layer. The lower via opening being in communication with the upper trench opening. Wherein the upper trench opening and the lower via opening comprise an aligned dual damascene opening.

Abstract translation: 对准的双镶嵌开口结构，包括以下。 具有形成在其上的金属结构的结构。 金属结构上的图案层叠层; 所述层堆叠按升序包括：图案化的底部蚀刻停止层; 图案化的下介电材料层; 图案化的中间蚀刻停止层; 和图案化的中间介电材料层; 下部和中间介电层由相同的材料组成。 在图案化的底部蚀刻停止层和图案化的下部介电材料层中的上部沟槽开口; 以及图案化的中间蚀刻停止层和图案化的中间介电材料层中的下通孔开口。 下通道开口与上沟槽开口连通。 其中上沟槽开口和下通孔开口包括对准的双镶嵌开口。