公开(公告)号：US06228770B1

公开(公告)日：2001-05-08

申请号：US09531784

申请日：2000-03-21

申请人： Yelehanka Ramachandramurthy Pradeep ,  Vijai Kumar Chhagan ,  Henry Gerung ,  Madhusudan Mukhopadhyay

发明人： Yelehanka Ramachandramurthy Pradeep ,  Vijai Kumar Chhagan ,  Henry Gerung ,  Madhusudan Mukhopadhyay

IPC分类号： H01L2100

CPC分类号： H01L21/7682

摘要： A new method of forming metal interconnects with air gaps between adjacent interconnects in the manufacture of an integrated circuit device is achieved. A semiconductor substrate is provided. The metal interconnects are formed overlying the semiconductor substrate. A silicon nitride liner layer is deposited. A gap filling oxide layer is deposited to fill gaps between adjacent metal interconnects. The gap filling oxide layer is polished down to the silicon nitride liner layer. A silicon nitride thin layer is deposited. The silicon nitride thin layer is patterned using an oversized, reverse mask of the metal interconnects. The patterning of the silicon nitride thin layer creates openings to thereby expose a portion of the gap filling oxide. The gap filling oxide layer is etched away. A self-sealing oxide layer is deposited overlying the silicon nitride thin layer and the silicon nitride liner layer. The self-sealing oxide layer seals over the gaps between the silicon nitride thin layer and the silicon nitride liner layer to thereby form permanent air gaps between the adjacent metal interconnects, and the integrated circuit is completed.

摘要翻译： 实现了在制造集成电路器件中在相邻互连之间形成具有气隙的金属互连的新方法。 提供半导体衬底。 金属互连形成在半导体衬底上。 沉积氮化硅衬垫层。 沉积间隙填充氧化物层以填充相邻的金属互连之间的间隙。 间隙填充氧化物层被抛光到氮化硅衬垫层。 沉积氮化硅薄层。 使用金属互连的过大的反向掩模来对氮化硅薄层进行构图。 氮化硅薄层的图案化形成开口，从而暴露间隙填充氧化物的一部分。 间隙填充氧化物层被蚀刻掉。 沉积氮化硅薄层和氮化硅衬层的自密封氧化层。 自密封氧化物层在氮化硅薄层和氮化硅衬垫层之间的间隙上密封，从而在相邻的金属互连之间形成永久的气隙，并且完成集成电路。

公开(公告)号：US06387765B2

公开(公告)日：2002-05-14

申请号：US09946982

申请日：2001-09-06

申请人： Vijai Kumar Chhagan ,  Yelehanka Ramachandramurthy Pradeep ,  Mei Sheng Zhou ,  Henry Gerung ,  Simon Chooi

发明人： Vijai Kumar Chhagan ,  Yelehanka Ramachandramurthy Pradeep ,  Mei Sheng Zhou ,  Henry Gerung ,  Simon Chooi

IPC分类号： H01L21336

CPC分类号： H01L29/66545 ,  H01L21/28044 ,  H01L21/28114 ,  H01L29/41 ,  H01L29/42376 ,  H01L29/4941

摘要： A method for forming an extended metal gate without poly wrap around effects. A semiconductor structure is provided having a gate structure thereon. The gate structure comprising a gate dielectric layer, a gate silicon layer, a doped silicon oxide layer, and a disposable gate layer stacked sequentially. Spacers are formed on the sidewalls of the gate structure. A dielectric gapfill layer is formed over the semiconductor structure and the gate structure and planarized, stopping on the disposable gate layer. A first silicon nitride layer is formed over the disposable gate layer, and a dielectric layer is formed over the first silicon nitride layer. The dielectric layer is patterned to form a trench over the gate structure; therein the trench has a width greater than the width of the gate structure. The first silicon nitride layer in the bottom of the trench and the disposable gate layer are removed using one or more selective etching processes. The doped silicon oxide layer is removed using an etch with a high selectivity of doped silicon oxide to undoped silicon oxide. A barrier layer is formed over the gate silicon layer, and a metal gate layer is formed on the barrier layer; whereby the metal gate layer has a greater width than the gate structure.

摘要翻译： 一种用于形成不具有聚环绕效应的延伸金属栅极的方法。 提供其上具有栅极结构的半导体结构。 栅极结构包括依次堆叠的栅极介电层，栅极硅层，掺杂氧化硅层和一次性栅极层。 隔板形成在栅极结构的侧壁上。 在半导体结构和栅极结构之上形成电介质间隙填充层，并在一次性栅极层上停止平坦化。 在一次性栅极层上形成第一氮化硅层，并且在第一氮化硅层上形成电介质层。 图案化电介质层以在栅极结构上形成沟槽; 其中沟槽的宽度大于栅极结构的宽度。 使用一个或多个选择性蚀刻工艺去除沟槽底部中的第一氮化硅层和一次性栅极层。 使用掺杂的氧化硅对未掺杂的氧化硅具有高选择性的蚀刻来去除掺杂的氧化硅层。 在栅极硅层上形成阻挡层，在阻挡层上形成金属栅极层; 由此金属栅极层具有比栅极结构更大的宽度。

公开(公告)号：US06337262B1

公开(公告)日：2002-01-08

申请号：US09519611

申请日：2000-03-06

申请人： Yelehanka Ramachandramurthy Pradeep ,  Chivukula Subrahmanyam ,  Vijai Kumar Chhagan ,  Henry Gerung

发明人： Yelehanka Ramachandramurthy Pradeep ,  Chivukula Subrahmanyam ,  Vijai Kumar Chhagan ,  Henry Gerung

IPC分类号： H01L2128

CPC分类号： H01L29/66583 ,  H01L21/28114 ,  H01L29/66553

摘要： A new method is provided for the integration of the of T-top gate process. Active regions are defined and bounded by STI's on the surface of a substrate. The pad oxide is removed from the substrate and replaced by a layer of SAC oxide. A thin layer of nitride is deposited that covers the surface of the created layer of SAC oxide and the surface of the STI regions. A layer of TEOS is deposited and etched defining the regions where the gate electrodes need to be formed. Gate spacers are next formed on the sidewalls of the openings that have been created in the layer of TEOS. The required implants (such as channel implant and threshold implant) are performed, the gate structure is then grown in the openings that have been created in the layer of TEOS. After the gate structure has been completed, the surface of the created structure is polished and the remaining layer of TEOS is removed. Source and drain regions implants can now be performed, LDD regions are implanted using a tilted implant. This tilted implant penetrates underneath the body of the created gate structures thereby creating the LDD regions. The removal of the layer of TEOS leaves in place the gate structures, one such structure is located in the active region of the surface of the substrate, two additional structures that have been created on the surface of the STI regions.

摘要翻译： 提供了一种用于集成T-top门过程的新方法。 有源区域由衬底表面上的STI限定和界定。 衬垫氧化物从衬底上去除并被一层SAC氧化物代替。 沉积薄层的氮化物，其覆盖所形成的SAC氧化物层的表面和STI区域的表面。 沉积和蚀刻一层TEOS，限定需要形成栅电极的区域。 接下来，在已经在TEOS层中形成的开口的侧壁上形成栅极间隔物。 执行所需的植入物（例如通道植入和阈值植入），然后在已经在TEOS层中产生的开口中生长栅极结构。 在栅极结构完成之后，对所形成的结构的表面进行抛光并除去TEOS的剩余层。 现在可以执行源极和漏极区域植入，使用倾斜植入物植入LDD区域。 这种倾斜的植入物渗透在所产生的栅极结构的主体下面，从而形成LDD区域。 TEOS层的去除留下了栅极结构，一个这样的结构位于衬底的表面的有源区域中，在STI区域的表面上产生了两个另外的结构。

公开(公告)号：US06391732B1

公开(公告)日：2002-05-21

申请号：US09595061

申请日：2000-06-16

申请人： Subhash Gupta ,  Yelehanka Ramachandramurthy ,  Vijai Kumar Chhagan

发明人： Subhash Gupta ,  Yelehanka Ramachandramurthy ,  Vijai Kumar Chhagan

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/266 ,  H01L21/31116 ,  H01L29/6656 ,  H01L29/7833

摘要： A new method of forming silicon nitride sidewall spacers has been achieved. In addition, a new device profile for a silicon nitride sidewall spacer has been achieved. An isolation region is provided overlying a semiconductor substrate. Polysilicon traces are provided. A liner oxide layer is formed overlying the polysilicon traces and the insulator layer. A silicon nitride layer is formed overlying the liner oxide layer. A polysilicon or amorphous silicon layer is deposited overlying the silicon nitride layer. The polysilicon or amorphous silicon layer is completely oxidized to form a temporary silicon dioxide layer. The temporary silicon dioxide layer is rounded in the corners due to volume expansion during the oxidation step. The temporary silicon dioxide layer is anisotropically etched through to expose horizontal surfaces of the silicon nitride layer while leaving vertical sidewalls of the temporary silicon dioxide layer. The silicon nitride layer is anisotropically etched to form silicon nitride sidewall spacers with an L-shaped profile. The integrated circuit device is completed.

摘要翻译： 已经实现了形成氮化硅侧壁间隔物的新方法。 此外，已经实现了用于氮化硅侧壁间隔物的新的器件配置。 设置在半导体衬底上的隔离区域。 提供多晶硅痕迹。 在多晶硅迹线和绝缘体层上形成衬里氧化物层。 形成覆盖衬垫氧化物层的氮化硅层。 沉积氮化硅层上的多晶硅或非晶硅层。 多晶硅或非晶硅层被完全氧化以形成临时二氧化硅层。 在氧化步骤期间由于体积膨胀，临时二氧化硅层在角部被倒圆。 临时二氧化硅层被各向异性地蚀刻以暴露氮化硅层的水平表面，同时留下临时二氧化硅层的垂直侧壁。 氮化硅层被各向异性蚀刻以形成具有L形轮廓的氮化硅侧壁间隔物。 集成电路装置完成。

公开(公告)号：US06534393B1

公开(公告)日：2003-03-18

申请号：US09236487

申请日：1999-01-25

申请人： Mei Sheng Zhou ,  Vijai Kumar Chhagan ,  Jian Xun Li

发明人： Mei Sheng Zhou ,  Vijai Kumar Chhagan ,  Jian Xun Li

IPC分类号： H01L214763

CPC分类号： H01L21/76895

摘要： A method for making low sheet resistance local metal interconnections and improved transistor performance is described. The method involves patterning a polysilicon layer and a silicon nitride (Si3N4) cap layer over device areas to form FET gate electrodes, and the patterned polysilicon extends over the field oxide regions to form portions of the local interconnections. After forming source/drain areas and sidewall spacers on the FET gate electrodes, a silicon oxide (SiO2) insulating layer is deposited and polished back to the Si3N4 cap. The Si3N4 is then selectively removed over the patterned polysilicon layer, leaving recesses in the SiO2 layer. After etching contact openings in the SiO2 layer to the substrate, a high electrically conducting metal layer, having a barrier layer, is deposited and patterned to complete the local interconnections. Portions of the metal are retained in the recesses over the pattered polysilicon layer to improve transistor performance, while portions of the metal in the contact openings provide low-contact resistance to the substrate.

摘要翻译： 描述了制造低电阻局部金属互连和改进的晶体管性能的方法。 该方法包括在器件区域上图案化多晶硅层和氮化硅（Si 3 N 4）覆盖层以形成FET栅电极，并且图案化的多晶硅在场氧化物区域上延伸以形成局部互连的部分。 在FET栅电极上形成源极/漏极区域和侧壁间隔物之后，将氧化硅（SiO 2）绝缘层沉积并抛光回Si 3 N 4帽。 然后在图案化的多晶硅层上选择性地去除Si 3 N 4，在SiO 2层中留下凹陷。 在将SiO 2层中的接触开口蚀刻到衬底之后，沉积具有阻挡层的高导电金属层并构图以完成局部互连。 金属的一部分保留在图案化的多晶硅层上的凹槽中以提高晶体管性能，而接触开口中的金属部分提供对基板的低接触电阻。