公开(公告)号：US06534393B1

公开(公告)日：2003-03-18

申请号：US09236487

申请日：1999-01-25

申请人： Mei Sheng Zhou ,  Vijai Kumar Chhagan ,  Jian Xun Li

发明人： Mei Sheng Zhou ,  Vijai Kumar Chhagan ,  Jian Xun Li

IPC分类号： H01L214763

CPC分类号： H01L21/76895

摘要： A method for making low sheet resistance local metal interconnections and improved transistor performance is described. The method involves patterning a polysilicon layer and a silicon nitride (Si3N4) cap layer over device areas to form FET gate electrodes, and the patterned polysilicon extends over the field oxide regions to form portions of the local interconnections. After forming source/drain areas and sidewall spacers on the FET gate electrodes, a silicon oxide (SiO2) insulating layer is deposited and polished back to the Si3N4 cap. The Si3N4 is then selectively removed over the patterned polysilicon layer, leaving recesses in the SiO2 layer. After etching contact openings in the SiO2 layer to the substrate, a high electrically conducting metal layer, having a barrier layer, is deposited and patterned to complete the local interconnections. Portions of the metal are retained in the recesses over the pattered polysilicon layer to improve transistor performance, while portions of the metal in the contact openings provide low-contact resistance to the substrate.

摘要翻译： 描述了制造低电阻局部金属互连和改进的晶体管性能的方法。 该方法包括在器件区域上图案化多晶硅层和氮化硅（Si 3 N 4）覆盖层以形成FET栅电极，并且图案化的多晶硅在场氧化物区域上延伸以形成局部互连的部分。 在FET栅电极上形成源极/漏极区域和侧壁间隔物之后，将氧化硅（SiO 2）绝缘层沉积并抛光回Si 3 N 4帽。 然后在图案化的多晶硅层上选择性地去除Si 3 N 4，在SiO 2层中留下凹陷。 在将SiO 2层中的接触开口蚀刻到衬底之后，沉积具有阻挡层的高导电金属层并构图以完成局部互连。 金属的一部分保留在图案化的多晶硅层上的凹槽中以提高晶体管性能，而接触开口中的金属部分提供对基板的低接触电阻。

公开(公告)号：US6140206A

公开(公告)日：2000-10-31

申请号：US332425

申请日：1999-06-14

申请人： Jian Xun Li ,  Qing Hua Zhong ,  Mei Sheng Zhou

发明人： Jian Xun Li ,  Qing Hua Zhong ,  Mei Sheng Zhou

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A method of forming a shallow trench isolation trenches in a silicon substrate of an integrated circuit device is achieved. A silicon substrate is provided. A buffer layer is deposited overlying the silicon substrate. An etching endpoint layer is deposited overlying the buffer layer. A silicon layer is deposited layer overlying the etching endpoint layer. A photoresist layer is coated overlying the silicon layer. The photoresist layer is developed wherein the photoresist layer is removed where the trenches are planned. The silicon layer, the etching endpoint layer, and the buffer layer are etched through to expose the top surface of the silicon substrate. The silicon layer and the silicon substrate layer are etched until the top surface of the etching endpoint layer is exposed, and the trenches are thereby formed. The integrated circuit device is completed.

摘要翻译： 实现了在集成电路器件的硅衬底中形成浅沟槽隔离沟槽的方法。 提供硅衬底。 沉积在硅衬底上的缓冲层。 沉积在缓冲层上的蚀刻端点层。 硅层是沉积在覆盖蚀刻终点层上的层。 涂覆在硅层上的光致抗蚀剂层。 显影光致抗蚀剂层，其中在规划沟槽的情况下去除光致抗蚀剂层。 蚀刻硅层，蚀刻终点层和缓冲层以露出硅衬底的顶表面。 蚀刻硅层和硅衬底层，直到蚀刻终点层的顶表面露出，从而形成沟槽。 集成电路装置完成。

公开(公告)号：US06524963B1

公开(公告)日：2003-02-25

申请号：US09421510

申请日：1999-10-20

申请人： Mei Sheng Zhou ,  Simon Chooi ,  Jian Xun Li

发明人： Mei Sheng Zhou ,  Simon Chooi ,  Jian Xun Li

IPC分类号： H01L21302

CPC分类号： H01L21/31116 ,  H01L21/02118 ,  H01L21/0212 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/31138 ,  H01L21/312 ,  H01L21/76802

摘要： A method etching an organic-based, low dielectric constant material in the manufacture of an integrated circuit device has been achieved. Organic materials without silicon and organic materials without fluorine can be etched by using, for example, hydrazine or ammonia gas. Organic materials with silicon can also be etched with the addition of a fluorine-containing or chlorine-containing gas. A semiconductor substrate is provided. A low dielectric constant organic-based material is deposited overlying the semiconductor substrate. The low dielectric constant organic-based material is etched to form desirable features using a plasma containing a gas comprising a nitrogen and hydrogen containing molecule, and the integrated circuit device is completed.

摘要翻译： 已经实现了在制造集成电路器件中蚀刻有机基低介电常数材料的方法。 不含硅的有机材料和无氟的有机材料可以通过使用例如肼或氨气进行蚀刻。 也可以通过添加含氟或含氯气体来蚀刻具有硅的有机材料。 提供半导体衬底。 沉积在半导体衬底上的低介电常数有机基材料。 使用包含含有氮和氢的分子的气体的等离子体来蚀刻低介电常数有机基材料以形成期望的特征，并且完成集成电路器件。

公开(公告)号：US5948701A

公开(公告)日：1999-09-07

申请号：US902846

申请日：1997-07-30

申请人： Simon Chooi ,  Mei-Sheng Zhou ,  Jian Xun Li

发明人： Simon Chooi ,  Mei-Sheng Zhou ,  Jian Xun Li

IPC分类号： H01L21/311 ,  H01L21/60 ,  H01L21/768 ,  H01L21/3065

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76804

摘要： A method for forming a via through a dielectric layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed upon the substrate a pair of microelectronic structures. There is then formed sequentially upon the substrate including the pair of microelectronic structures a first conformal dielectric layer followed by a second conformal dielectric layer followed by a third dielectric layer, where the second conformal dielectric layer serves as an etch stop layer with respect to the third dielectric layer in a first plasma etch method employed in forming in part a via through the third dielectric layer, the second conformal dielectric layer and the first conformal dielectric layer at a location between the pair of microelectronic structures. The first plasma etch method employs an etchant gas composition which forms a passivating fluorocarbon polymer layer upon non-horizontal portions of the third dielectric layer, the second conformal dielectric layer and the first conformal dielectric layer. There is then formed upon the third dielectric layer a patterned photoresist layer which defines the location between the pair of structures to be formed the via through the third dielectric layer, the second conformal dielectric layer and the first conformal dielectric layer. There is then etched through the first plasma etch method the third dielectric layer and the second conformal dielectric layer to form a partial via while forming the passivating fluorocarbon polymer layer upon non-horizontal portions of the third dielectric layer, the second conformal dielectric layer and the first dielectric layer. Finally, there is then etched through a second plasma etch method the first conformal dielectric layer to form the via through the third dielectric layer, the second conformal dielectric layer and the first conformal dielectric layer.

摘要翻译： 在微电子学制造中通过介电层形成通孔的方法。 首先提供了在微电子制造中使用的衬底。 然后在衬底上形成一对微电子结构。 然后在包括一对微电子结构的基板上依次形成第一共形介电层，随后是第二共形介电层，随后是第三介电层，其中第二共形绝缘层用作相对于第三绝缘层的蚀刻停止层 在第一等离子体蚀刻方法中使用的介电层，其用于在所述一对微电子结构之间的位置处部分地通过所述第三介电层，所述第二共形介电层和所述第一共形介电层形成通孔。 第一等离子体蚀刻方法采用蚀刻剂气体组合物，其在第三介电层，第二共形介电层和第一共形介电层的非水平部分上形成钝化氟碳聚合物层。 然后在第三电介质层上形成图案化的光致抗蚀剂层，该图案化的光致抗蚀剂层限定通过第三介电层，第二共形介电层和第一共形介电层形成通孔的一对结构之间的位置。 然后通过第一等离子体蚀刻方法蚀刻第三介电层和第二共形介电层以形成部分通孔，同时在第三介电层，第二共形介电层和第二保形介电层的非水平部分上形成钝化氟碳聚合物层 第一电介质层。 最后，然后通过第二等离子体蚀刻方法蚀刻第一共形介电层，以通过第三介电层，第二共形介电层和第一共形介电层形成通孔。

公开(公告)号：US5930627A

公开(公告)日：1999-07-27

申请号：US851403

申请日：1997-05-05

申请人： Mei Sheng Zhou ,  Sheau-Tan Loong ,  Koon Lay Denise Tan ,  Jian Xun Li ,  Wing Hong Chiu ,  Kok Hiang Stephanie Tang

发明人： Mei Sheng Zhou ,  Sheau-Tan Loong ,  Koon Lay Denise Tan ,  Jian Xun Li ,  Wing Hong Chiu ,  Kok Hiang Stephanie Tang

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521

摘要： Silicon enriched silicon oxynitride is used in applications both as an independent etch stop and as a cap layer and sidewall component over polysilicon gate electrodes in order to prevent insulator thinning and shorts caused by a mis-aligned contact mask. In one embodiment a silicon enriched silicon oxynitride layer is placed over a polysilicon gate with conventional sidewalls and insulative cap. In another embodiment the insulative cap and the sidewalls are formed of a silicon enriched silicon oxinitride. Etching of contact openings in the subsequently deposited insulative layer is suppressed by the silicon enriched silicon oxynitride if it is engaged because of a mis-aligned contact mask. In another embodiment a polysilicon stack edge of a memory device is protected by a conformal silicon oxynitride layer during etching of a self-aligned-source (SAS) region. These embodiments are accomplished with minimal and virtually negligible increase in process complexity or cost.

摘要翻译： 富含硅的氮氧化硅被用作独立的蚀刻停止层以及作为多晶硅栅极电极上的覆盖层和侧壁部件的应用，以便防止由错配对接触掩模引起的绝缘体变薄和短路。 在一个实施例中，将富硅氧氮化硅层放置在具有常规侧壁和绝缘帽的多晶硅栅极上。 在另一个实施例中，绝缘帽和侧壁由富硅硅氮化硅形成。 如果由于不对准的接触掩模而被接合，则由富硅氧氮化物抑制随后沉积的绝缘层中的接触开口的蚀刻。 在另一个实施例中，在自对准源（SAS）区域的蚀刻期间，存储器件的多晶硅堆叠边缘被保形氮氧化硅层保护。 这些实施例以过程复杂性或成本的最小和几乎可忽略的增加来实现。

公开(公告)号：US07238971B2

公开(公告)日：2007-07-03

申请号：US11123748

申请日：2005-05-04

申请人： Jian Xun Li ,  Lap Chan ,  Purakh Raj Verma ,  Jia Zhen Zheng ,  Shao-fu Sanford Chu

发明人： Jian Xun Li ,  Lap Chan ,  Purakh Raj Verma ,  Jia Zhen Zheng ,  Shao-fu Sanford Chu

IPC分类号： H01L29/732

CPC分类号： H01L29/66242 ,  H01L29/737

摘要： A lateral heterojunction bipolar transistor (HBT) comprising a semiconductor substrate having having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.

摘要翻译： 一种横向异质结双极晶体管（HBT），包括在半导体衬底上具有第一绝缘层的半导体衬底。 基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。 半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。 基底结构形成在基底沟槽中。 通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。 基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

公开(公告)号：US07022578B2

公开(公告)日：2006-04-04

申请号：US10683713

申请日：2003-10-09

申请人： Purakh Raj Verma ,  Shao-fu Sanford Chu ,  Lap Chan ,  Jian Xun Li ,  Zhen Jia Zheng

发明人： Purakh Raj Verma ,  Shao-fu Sanford Chu ,  Lap Chan ,  Jian Xun Li ,  Zhen Jia Zheng

IPC分类号： H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/7378

摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therefor, comprising a semiconductor substrate having a collector region, an intrinsic base region of a compound semiconductive material over the collector region, an extrinsic base region, an emitter structure, an interlevel dielectric layer over the collector region, extrinsic base region and emitter structure, and connections through the interlevel dielectric layer to the base region, the emitter structure, and the collector region. The emitter structure is formed by forming a reverse emitter window over the intrinsic base region, which subsequently is etched to form an emitter window having a multi-layer reverse insulating spacer therein.

摘要翻译： 一种异质结双极晶体管（HBT）及其制造方法，包括具有集电极区域，集电极区域上的化合物半导体材料的本征基极区域，非本征基极区域，发射极结构，层间电介质层 集电极区域，非本征基极区域和发射极结构以及通过层间介质层到基极区域，发射极结构和集电极区域的连接。 通过在本征基极区域上形成反向发射极窗口形成发射极结构，其随后被蚀刻以形成其中具有多层反向绝缘间隔物的发射极窗口。

公开(公告)号：US06972237B2

公开(公告)日：2005-12-06

申请号：US10725670

申请日：2003-12-01

申请人： Purakh Raj Verma ,  Shao-fu Sanford Chu ,  Lap Chan ,  Jia Zhen Zheng ,  Jian Xun Li

发明人： Purakh Raj Verma ,  Shao-fu Sanford Chu ,  Lap Chan ,  Jia Zhen Zheng ,  Jian Xun Li

IPC分类号： H01L21/331 ,  H01L29/737 ,  H01L21/8222

CPC分类号： H01L29/66242 ,  H01L29/737

摘要： A method for manufacturing a heterojunction bipolar transistor is provided. An intrinsic collector structure is formed on a substrate. An extrinsic base structure partially overlaps the intrinsic collector structure. An intrinsic base structure is formed adjacent the intrinsic collector structure and under the extrinsic base structure. An emitter structure is formed adjacent the intrinsic base structure. An extrinsic collector structure is formed adjacent the intrinsic collector structure. A plurality of contacts is formed through an interlevel dielectric layer to the extrinsic collector structure, the extrinsic base structure, and the emitter structure.

公开(公告)号：US06395631B1

公开(公告)日：2002-05-28

申请号：US09366751

申请日：1999-08-04

申请人： Yi Xu ,  Jian Xun Li

发明人： Yi Xu ,  Jian Xun Li

IPC分类号： H01L214763

CPC分类号： H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/7688

摘要： A method for forming, within a low dielectric constant dielectric layer formed upon a substrate employed within a microelectronics fabrication, a conductor pattern employing a hard mask cap layer. There is first provided a substrate having conductor regions formed therein upon which is formed a low dielectric constant dielectric layer. There is then formed over the substrate a silicon containing hard mask cap layer. There is then formed over the hard mask cap layer a patterned photoresist etch mask layer. There is then subtractively etched employing the patterned photoresist etch mask layer and a first subtractive etching environment the pattern into the hard mask layer. There is then subtractively etched employing the patterned hard mask layer and a second etching environment the pattern into the low dielectric constant dielectric layer, simultaneously stripping the photoresist etch mask layer. There is then removed by delamination the hard mask cap layer employing a chemical treatment, leaving a trench pattern in the low dielectric constant dielectric layer. The trench pattern may be filled with a microelectronics material to form a patterned layer around which is a maximized amount of low dielectric constant dielectric material. The order of filling with microelectronics material and delamination of the hard mask layer may be reversed if desired to minimize the amount of patterned microelectronics material remaining above the substrate surface, in which case the method is a lift off method for patterning a microelectronics layer. After filling and patterning, the substrate surface may be planarized for further processing and optional additional microelectronics layers formed thereover.

摘要翻译： 在形成在微电子制造中使用的衬底上的低介电常数电介质层内形成使用硬掩模帽层的导体图案的方法。 首先，设置有形成有导体区域的基板，在其上形成低介电常数介电层。 然后在衬底上形成含硅的硬掩模帽层。 然后在硬掩模帽层上形成图案化的光致抗蚀剂蚀刻掩模层。 然后使用图案化的光致抗蚀剂蚀刻掩模层进行减法蚀刻，并且将图案的第一减去刻蚀环境刻蚀成硬掩模层。 然后使用图案化的硬掩模层进行减法蚀刻，并且将图案的第二蚀刻环境放置到低介电常数介电层中，同时剥离光致抗蚀剂蚀刻掩模层。 然后通过分层去除采用化学处理的硬掩模帽层，在低介电常数介电层中留下沟槽图案。 沟槽图案可以用微电子材料填充以形成图案化层，围绕其形成最大量的低介电常数电介质材料。 如果需要，微电子材料的填充顺序和硬掩模层的分层可以相反，以使在基板表面之上残留的图案化微电子材料的量最小化，在这种情况下，该方法是用于图案化微电子层的剥离方法。 在填充和图案化之后，衬底表面可以被平坦化以用于进一步处理，并且在其上形成可选的另外的微电子层。

公开(公告)号：US07049201B2

公开(公告)日：2006-05-23

申请号：US10703297

申请日：2003-11-06

申请人： Purakh Raj Verma ,  Shao-Fu Sanford Chu ,  Lap Chan ,  Jian Xun Li ,  Jia Zhen Zheng

发明人： Purakh Raj Verma ,  Shao-Fu Sanford Chu ,  Lap Chan ,  Jian Xun Li ,  Jia Zhen Zheng

IPC分类号： H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therefor, comprising a semiconductor substrate having a collector region, a number of insulating layers over the semiconductor substrate, at least one of the number of insulating layers having a base cavity over the collector region, a base structure of a compound semiconductive material in the base cavity, a window in the insulating layer over the base cavity, an emitter structure in the window, an interlevel dielectric layer, and connections through the interlevel dielectric layer to the base structure, the emitter structure, and the collector region. The base structure and the emitter structure preferably are formed in the same processing chamber.

摘要翻译： 一种异质结双极晶体管（HBT）及其制造方法，包括具有集电极区域，半导体衬底上的多个绝缘层的半导体衬底，在集电极区域上具有基腔的多个绝缘层中的至少一个， 基腔中的复合半导体材料的基底结构，在基底腔上的绝缘层中的窗口，窗口中的发射极结构，层间介电层以及通过层间介电层到基底结构的连接，发射极 结构和收集器区域。 基底结构和发射极结构优选地形成在相同的处理室中。