Method and Apparatus of Performing An Erase Operation On A Memory Integrated Circuit
    1.
    发明申请
    Method and Apparatus of Performing An Erase Operation On A Memory Integrated Circuit 有权
    在存储器集成电路中执行擦除操作的方法和装置

    公开(公告)号:US20120300553A1

    公开(公告)日:2012-11-29

    申请号:US13567817

    申请日:2012-08-06

    IPC分类号: G11C16/04

    摘要: Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.

    摘要翻译: 各种讨论的方法改进了过度擦除问题和耦合效应,并且包括(A)(i)擦除组的第一外部选定字线之间的多电平接触,以及(ii)与易失性组相邻的第一未选择字线 第一外选字线; (B)在(i)擦除组的第一外部选择字线之间的足够的间隔距离,和(ii)与第一外部选择字线相邻的容易组之外的第一未选择字线。 这些是将(i)擦除组的第一外部选择的字线从(ii)与第一外部选择字线相邻的易用组之外的第一未选择字线电隔离的示例。

    Method and apparatus of performing an erase operation on a memory integrated circuit
    2.
    发明授权
    Method and apparatus of performing an erase operation on a memory integrated circuit 有权
    在存储器集成电路上执行擦除操作的方法和装置

    公开(公告)号:US08259499B2

    公开(公告)日:2012-09-04

    申请号:US12826280

    申请日:2010-06-29

    IPC分类号: G11C11/34

    摘要: Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.

    摘要翻译: 各种讨论的方法改进了过度擦除问题和耦合效应,并且包括(A)(i)擦除组的第一外部选定字线之间的多电平接触,以及(ii)与易失性组相邻的第一未选择字线 第一外选字线; (B)在(i)擦除组的第一外部选择字线之间的足够的间隔距离,和(ii)与第一外部选择字线相邻的容易组之外的第一未选择字线。 这些是将(i)擦除组的第一外部选择的字线从(ii)与第一外部选择字线相邻的易用组之外的第一未选择字线电隔离的示例。

    Method and Apparatus of Performing An Erase Operation on a Memory Integrated Circuit
    3.
    发明申请
    Method and Apparatus of Performing An Erase Operation on a Memory Integrated Circuit 有权
    在存储器集成电路上执行擦除操作的方法和装置

    公开(公告)号:US20110317493A1

    公开(公告)日:2011-12-29

    申请号:US12826280

    申请日:2010-06-29

    IPC分类号: G11C16/04

    摘要: Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.

    摘要翻译: 各种讨论的方法改进了过度擦除问题和耦合效应,并且包括(A)(i)擦除组的第一外部选定字线之间的多电平接触,以及(ii)与易失性组相邻的第一未选择字线 第一外选字线; (B)在(i)擦除组的第一外部选择字线之间的足够的间隔距离,和(ii)与第一外部选择字线相邻的容易组之外的第一未选择字线。 这些是将(i)擦除组的第一外部选择的字线从(ii)与第一外部选择字线相邻的易用组之外的第一未选择字线电隔离的示例。

    Method and apparatus of performing an erase operation on a memory integrated circuit
    4.
    发明授权
    Method and apparatus of performing an erase operation on a memory integrated circuit 有权
    在存储器集成电路上执行擦除操作的方法和装置

    公开(公告)号:US08508993B2

    公开(公告)日:2013-08-13

    申请号:US13567817

    申请日:2012-08-06

    IPC分类号: G11C11/34

    摘要: Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.

    摘要翻译: 各种讨论的方法改进了过度擦除问题和耦合效应,并且包括(A)(i)擦除组的第一外部选定字线之间的多电平接触,以及(ii)与易失性组相邻的第一未选择字线 第一外选字线; (B)在(i)擦除组的第一外部选择字线之间的足够的间隔距离,和(ii)与第一外部选择字线相邻的容易组之外的第一未选择字线。 这些是将(i)擦除组的第一外部选择的字线从(ii)与第一外部选择字线相邻的易用组之外的第一未选择字线电隔离的示例。

    Non-volatile integrated circuit having read while write capability using one address register
    5.
    发明授权
    Non-volatile integrated circuit having read while write capability using one address register 有权
    具有读写能力的非易失性集成电路使用一个地址寄存器

    公开(公告)号:US06178132B1

    公开(公告)日:2001-01-23

    申请号:US09391917

    申请日:1999-09-09

    IPC分类号: G11C800

    CPC分类号: G11C16/08 G11C2216/22

    摘要: A non-volatile integrated circuit memory, such as a flash memory device based on floating gate transistor memory cells, with read while write capability is provided using a single address register. The integrated circuit includes at least two independent arrays of memory cells. During a program or an erase operation in one array on the non-volatile integrated circuit, a read operation can be executed in the other array on the same integrated circuit by bypassing the address register altogether, and allowing the register to remain in use by the program or erase operation. A bypass combinatorial logic path for the read process is coupled to the same address inputs as the address register, and operable in parallel with the registered address path.

    摘要翻译: 使用单个地址寄存器来提供非易失性集成电路存储器,例如基于浮栅晶体管存储器单元的闪速存储器件,具有读写能力。 集成电路包括至少两个独立的存储单元阵列。 在非易失性集成电路中的一个阵列中的程序或擦除操作期间,可以通过绕过地址寄存器来在同一集成电路上的另一个阵列中执行读取操作,并允许寄存器由 编程或擦除操作。 用于读取处理的旁路组合逻辑路径被耦合到与地址寄存器相同的地址输入,并且与注册的地址路径并行操作。