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    Method and apparatus of performing an erase operation on a memory integrated circuit
    1.
    发明授权
    Method and apparatus of performing an erase operation on a memory integrated circuit 有权
    在存储器集成电路上执行擦除操作的方法和装置

    公开(公告)号：US08508993B2

    公开(公告)日：2013-08-13

    申请号：US13567817

    申请日：2012-08-06

    申请人： Yi-Fan Chang ,  Su-chueh Lo ,  Cheng-Ming Yi ,  Ta Kang Chu ,  Chu Ching Wu ,  Kuo Yu Liao ,  Ken Hui Chen ,  Kuen Long Chang ,  Chun Hsiung Hung

    发明人： Yi-Fan Chang ,  Su-chueh Lo ,  Cheng-Ming Yi ,  Ta Kang Chu ,  Chu Ching Wu ,  Kuo Yu Liao ,  Ken Hui Chen ,  Kuen Long Chang ,  Chun Hsiung Hung

    IPC分类号： G11C11/34

    CPC分类号： G11C11/5635 ,  G11C16/0483 ,  G11C16/3418

    摘要： Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.

    摘要翻译： 各种讨论的方法改进了过度擦除问题和耦合效应，并且包括（A）（i）擦除组的第一外部选定字线之间的多电平接触，以及（ii）与易失性组相邻的第一未选择字线 第一外选字线; （B）在（i）擦除组的第一外部选择字线之间的足够的间隔距离，和（ii）与第一外部选择字线相邻的容易组之外的第一未选择字线。 这些是将（i）擦除组的第一外部选择的字线从（ii）与第一外部选择字线相邻的易用组之外的第一未选择字线电隔离的示例。

    Method and Apparatus of Performing An Erase Operation on a Memory Integrated Circuit
    2.
    发明申请
    Method and Apparatus of Performing An Erase Operation on a Memory Integrated Circuit 有权
    在存储器集成电路上执行擦除操作的方法和装置

    公开(公告)号：US20110317493A1

    公开(公告)日：2011-12-29

    申请号：US12826280

    申请日：2010-06-29

    申请人： Yi-Fan Chang ,  Su-chueh Lo ,  Cheng Ming Yih ,  Ta Kang Chu ,  Chu Ching Wu ,  Kuo Yu Liao ,  Ken Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    发明人： Yi-Fan Chang ,  Su-chueh Lo ,  Cheng Ming Yih ,  Ta Kang Chu ,  Chu Ching Wu ,  Kuo Yu Liao ,  Ken Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5635 ,  G11C16/0483 ,  G11C16/3418

    摘要： Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.

    摘要翻译： 各种讨论的方法改进了过度擦除问题和耦合效应，并且包括（A）（i）擦除组的第一外部选定字线之间的多电平接触，以及（ii）与易失性组相邻的第一未选择字线 第一外选字线; （B）在（i）擦除组的第一外部选择字线之间的足够的间隔距离，和（ii）与第一外部选择字线相邻的容易组之外的第一未选择字线。 这些是将（i）擦除组的第一外部选择的字线从（ii）与第一外部选择字线相邻的易用组之外的第一未选择字线电隔离的示例。

    Method and apparatus of performing an erase operation on a memory integrated circuit
    3.
    发明授权
    Method and apparatus of performing an erase operation on a memory integrated circuit 有权
    在存储器集成电路上执行擦除操作的方法和装置

    公开(公告)号：US08259499B2

    公开(公告)日：2012-09-04

    申请号：US12826280

    申请日：2010-06-29

    申请人： Yi-Fan Chang ,  Su-chueh Lo ,  Cheng Ming Yih ,  Ta Kang Chu ,  Chu Ching Wu ,  Kuo Yu Liao ,  Ken Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    发明人： Yi-Fan Chang ,  Su-chueh Lo ,  Cheng Ming Yih ,  Ta Kang Chu ,  Chu Ching Wu ,  Kuo Yu Liao ,  Ken Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    IPC分类号： G11C11/34

    CPC分类号： G11C11/5635 ,  G11C16/0483 ,  G11C16/3418

    摘要： Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.

    摘要翻译： 各种讨论的方法改进了过度擦除问题和耦合效应，并且包括（A）（i）擦除组的第一外部选定字线之间的多电平接触，以及（ii）与易失性组相邻的第一未选择字线 第一外选字线; （B）在（i）擦除组的第一外部选择字线之间的足够的间隔距离，和（ii）与第一外部选择字线相邻的容易组之外的第一未选择字线。 这些是将（i）擦除组的第一外部选择的字线从（ii）与第一外部选择字线相邻的易用组之外的第一未选择字线电隔离的示例。

    Method and Apparatus of Performing An Erase Operation On A Memory Integrated Circuit
    4.
    发明申请
    Method and Apparatus of Performing An Erase Operation On A Memory Integrated Circuit 有权
    在存储器集成电路中执行擦除操作的方法和装置

    公开(公告)号：US20120300553A1

    公开(公告)日：2012-11-29

    申请号：US13567817

    申请日：2012-08-06

    申请人： Yi-Fan Chang ,  Su-chueh Lo ,  Cheng Ming Yih ,  Ta Kang Chu ,  Chu Ching Wu ,  Kuo Yu Liao ,  Ken Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    发明人： Yi-Fan Chang ,  Su-chueh Lo ,  Cheng Ming Yih ,  Ta Kang Chu ,  Chu Ching Wu ,  Kuo Yu Liao ,  Ken Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5635 ,  G11C16/0483 ,  G11C16/3418

    摘要： Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.

    摘要翻译： 各种讨论的方法改进了过度擦除问题和耦合效应，并且包括（A）（i）擦除组的第一外部选定字线之间的多电平接触，以及（ii）与易失性组相邻的第一未选择字线 第一外选字线; （B）在（i）擦除组的第一外部选择字线之间的足够的间隔距离，和（ii）与第一外部选择字线相邻的容易组之外的第一未选择字线。 这些是将（i）擦除组的第一外部选择的字线从（ii）与第一外部选择字线相邻的易用组之外的第一未选择字线电隔离的示例。

    Structures and methods for enhancing erase uniformity in an NROM array
    9.
    发明授权
    Structures and methods for enhancing erase uniformity in an NROM array 有权

    公开(公告)号：US07236404B2

    公开(公告)日：2007-06-26

    申请号：US11210425

    申请日：2005-08-24

    申请人： Ching Chung Lin ,  Ken Hui Chen ,  Nai Ping Kuo ,  Han Sung Chen ,  Chun Hsiung Hung ,  Wen Yi Hsieh

    发明人： Ching Chung Lin ,  Ken Hui Chen ,  Nai Ping Kuo ,  Han Sung Chen ,  Chun Hsiung Hung ,  Wen Yi Hsieh

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0491 ,  G11C16/0475 ,  G11C16/14

    摘要： A virtual ground NROM array has a matrix of NROM cells in which during an erase operation the non-erasing side of NROM cells are connected to a common node for enhancing the erase uniformity of the NROM array. If an operation requests erasing on the left side of NROM cells, a positive voltage is supplied from an internal power supply to the left side for each of the NROM cells, and the right side for each of the NROM cells is discharged to a common node. If an operation requests erasing the right side of NROM cells, a positive voltage is supplied from the internal power supply to the right side for each of the NROM cells, and the right side for each of the NROM cells is connected to the common node. The voltage level of the common mode is selected to be sufficiently high in order to prevent from punch through while at the same time sufficiently low to maintain the lateral electric field for erase operation to function optimally. In an alternative embodiment, non-erasing sides of NROM cells in the NROM array are connected to a current source during an erase operation for enhancing the erase uniformity of the NROM array. If an operation requests erasing the left side of NROM cells, a positive voltage is supplied from an internal power supply to the left side for each of the NROM cells, and the right side for each of the NROM cells is discharged to a current source. If an operation requests erasing the right side of NROM cells, a positive voltage is supplied from the internal power supply to the right side for each of the NROM cells, and the right side for each of the NROM cells is connected to the current source.

    Structures and methods for enhancing erase uniformity in a nitride read-only memory array
    10.
    发明授权
    Structures and methods for enhancing erase uniformity in a nitride read-only memory array 有权
    用于增强氮化物只读存储器阵列中的擦除均匀性的结构和方法

    公开(公告)号：US07423913B2

    公开(公告)日：2008-09-09

    申请号：US11695668

    申请日：2007-04-03

    申请人： Ching Chung Lin ,  Ken Hui Chen ,  Nai Ping Kuo ,  Han Sung Chen ,  Chun Hsiung Hung ,  Wen Yi Hsieh

    发明人： Ching Chung Lin ,  Ken Hui Chen ,  Nai Ping Kuo ,  Han Sung Chen ,  Chun Hsiung Hung ,  Wen Yi Hsieh

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0491 ,  G11C16/0475 ,  G11C16/14

    摘要： A virtual ground nitride read-only memory array has a matrix of nitride read-only memory cells in which during an erase operation the non-erasing side of nitride read-only memory cells are connected to a common node for enhancing the erase uniformity of the nitride read-only memory array. If an operation requests erasing on the left side of nitride read-only memory cells, a positive voltage is supplied from an internal power supply to the left side for each of the nitride read-only memory cells, and the right side for each of the nitride read-only memory cells is discharged to a common node. The voltage level of the common mode is selected to be sufficiently high in order to prevent from punch through while at the same time sufficiently low to maintain the lateral electric field for erase operation to function optimally.

    摘要翻译： 虚拟氮化物只读存储器阵列具有氮化物只读存储器单元的矩阵，其中在擦除操作期间，氮化物只读存储器单元的非擦除侧连接到公共节点，以增强擦除均匀性 氮化物只读存储器阵列。 如果操作要求在氮化物只读存储单元的左侧擦除，则从内部电源向氮化物只读存储单元中的每一个向左侧提供正电压，并且对于每个 氮化物只读存储单元被放电到公共节点。 选择共模的电压足够高以防止穿通，同时足够低以保持用于擦除操作的横向电场最佳地起作用。