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1.发明授权Method of trimming a hard mask layer, method for fabricating a gate in a MOS transistor, and a stack for fabricating a gate in a MOS transistor 有权修整硬掩模层的方法，在MOS晶体管中制造栅极的方法和用于制造MOS晶体管中的栅极的堆叠公开(公告)号：US07592265B2
公开(公告)日：2009-09-22
申请号：US11620028
申请日：2007-01-04
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/28123 , H01L21/0271 , H01L21/0332 , H01L21/0338 , H01L21/31116 , H01L21/31138 , H01L21/32139 , H01L21/7624 , H01L29/6659 , H01L29/7833 , Y10S438/947 , Y10S438/95
摘要： A method of trimming hard mask is provided. The method includes providing a substrate, a hard mask layer, and a tri-layer stack on the substrate. The tri-layer stack includes a top photo resist layer, a silicon photo resist layer, and a bottom photo resist layer. The top photo resist layer, the silicon photo resist layer, the bottom photo resist layer, and the hard mask layer are patterned sequentially. A trimming process is performed on the hard mask layer. The bottom photo resist layer of the present invention is thinner and loses some height in the etching process, so the bottom photo resist layer will not collapse.
摘要翻译： 提供了修剪硬掩模的方法。 该方法包括在衬底上提供衬底，硬掩模层和三层堆叠。 三层堆叠包括顶部光致抗蚀剂层，硅光致抗蚀剂层和底部光致抗蚀剂层。 顺序地对顶部光致抗蚀剂层，硅光致抗蚀剂层，底部光致抗蚀剂层和硬掩模层进行图案化。 在硬掩模层上进行修整处理。 本发明的底部光致抗蚀剂层在蚀刻工艺中更薄并且损失一些高度，因此底部光致抗蚀剂层将不会塌陷。
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2.发明申请METHOD OF TRIMMING A HARD MASK LAYER, METHOD FOR FABRICATING A GATE IN A MOS TRANSISTOR, AND A STACK FOR FABRICATING A GATE IN A MOS TRANSISTOR 审中-公开用于制造硬掩模层的方法，用于在MOS晶体管中形成栅极的方法，以及用于在MOS晶体管中形成栅极的堆叠公开(公告)号：US20090206403A1
公开(公告)日：2009-08-20
申请号：US12430107
申请日：2009-04-27
IPC分类号： H01L29/06
CPC分类号： H01L21/28123 , H01L21/0271 , H01L21/0332 , H01L21/0338 , H01L21/31116 , H01L21/31138 , H01L21/32139 , H01L21/7624 , H01L29/6659 , H01L29/7833 , Y10S438/947 , Y10S438/95
摘要： A stack structure for forming a gate of a MOS transistor includes a substrate including a plurality of shallow trench isolations therein; a dielectric layer, a conductive layer and a hard mask layer formed on the substrate in sequence; and a tri-layer stack comprising a top photo resist layer, a silicon-containing photo resist layer and a bottom anti-reflective coating (BARC) on the hard mask layer, wherein the silicon-containing photo resist layer comprises 10-30% silicon and the hard mask layer has a high etching selectivity ratio to the conductive layer.
摘要翻译： 用于形成MOS晶体管的栅极的堆叠结构包括其中包括多个浅沟槽隔离的衬底; 依次形成在基板上的电介质层，导电层和硬掩模层; 以及包括在所述硬掩模层上的顶部光致抗蚀剂层，含硅光刻胶层和底部抗反射涂层（BARC）的三层堆叠，其中所述含硅光致抗蚀剂层包括10-30％的硅 并且硬掩模层与导电层具有高蚀刻选择性比。
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公开(公告)号：US08071487B2
公开(公告)日：2011-12-06
申请号：US11464496
申请日：2006-08-15
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/0271 , H01L21/0332 , H01L21/3081 , H01L21/32139
摘要： A stacked structure for patterning a material layer to form an opening pattern with a predetermined opening width in the layer is provided. The stacked structure includes an underlayer, a silicon rich organic layer, and a photoresist layer. The underlayer is on the material layer. The silicon rich organic layer is between the underlayer and the photoresist layer. The thickness of the photoresist layer is smaller than that of the underlayer and larger than two times of the thickness of the silicon rich organic layer. The thickness of the underlayer is smaller than three times of the predetermined opening width.
摘要翻译： 提供了用于图案化材料层以形成在该层中具有预定开口宽度的开口图案的层叠结构。 层叠结构包括底层，富硅有机层和光致抗蚀剂层。 底层在材料层上。 富硅有机层位于底层和光刻胶层之间。 光致抗蚀剂层的厚度小于底层的厚度，并且大于富硅有机层的厚度的两倍。 底层的厚度小于预定开口宽度的三倍。
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公开(公告)号：US20110254142A1
公开(公告)日：2011-10-20
申请号：US13167737
申请日：2011-06-24
IPC分类号： H01L29/02
CPC分类号： H01L21/0271 , H01L21/0332 , H01L21/3081 , H01L21/32139
摘要： A stacked structure for patterning a material layer to form an opening pattern with a predetermined opening width in the layer is provided. The stacked structure includes an underlayer, a silicon rich organic layer, and a photoresist layer. The underlayer is on the material layer. The silicon rich organic layer is between the underlayer and the photoresist layer. The thickness of the photoresist layer is smaller than that of the underlayer and larger than two times of the thickness of the silicon rich organic layer. The thickness of the underlayer is smaller than three times of the predetermined opening width.
摘要翻译： 提供了用于图案化材料层以形成在该层中具有预定开口宽度的开口图案的层叠结构。 层叠结构包括底层，富硅有机层和光致抗蚀剂层。 底层在材料层上。 富硅有机层位于底层和光刻胶层之间。 光致抗蚀剂层的厚度小于底层的厚度，并且大于富硅有机层的厚度的两倍。 底层的厚度小于预定开口宽度的三倍。
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5.发明申请METHOD OF TRIMMING A HARD MASK LAYER, METHOD FOR FABRICATING A GATE IN A MOS TRANSISTOR, AND A STACK FOR FABRICATING A GATE IN A MOS TRANSISTOR 有权用于制造硬掩模层的方法，用于在MOS晶体管中形成栅极的方法，以及用于在MOS晶体管中形成栅极的堆叠公开(公告)号：US20080164526A1
公开(公告)日：2008-07-10
申请号：US11620028
申请日：2007-01-04
IPC分类号： H01L29/786 , G03F1/00 , H01L21/283
CPC分类号： H01L21/28123 , H01L21/0271 , H01L21/0332 , H01L21/0338 , H01L21/31116 , H01L21/31138 , H01L21/32139 , H01L21/7624 , H01L29/6659 , H01L29/7833 , Y10S438/947 , Y10S438/95
摘要： A method of trimming hard mask is provided. The method includes providing a substrate, a hard mask layer, and a tri-layer stack on the substrate. The tri-layer stack includes a top photo resist layer, a silicon photo resist layer, and a bottom photo resist layer. The top photo resist layer, the silicon photo resist layer, the bottom photo resist layer, and the hard mask layer are patterned sequentially. A trimming process is performed on the hard mask layer. The bottom photo resist layer of the present invention is thinner and loses some height in the etching process, so the bottom photo resist layer will not collapse.
摘要翻译： 提供了修剪硬掩模的方法。 该方法包括在衬底上提供衬底，硬掩模层和三层堆叠。 三层堆叠包括顶部光致抗蚀剂层，硅光致抗蚀剂层和底部光致抗蚀剂层。 顺序地对顶部光致抗蚀剂层，硅光致抗蚀剂层，底部光致抗蚀剂层和硬掩模层进行图案化。 在硬掩模层上进行修整处理。 本发明的底部光致抗蚀剂层在蚀刻工艺中更薄并且损失一些高度，因此底部光致抗蚀剂层将不会塌陷。
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公开(公告)号：US20080045033A1
公开(公告)日：2008-02-21
申请号：US11464496
申请日：2006-08-15
IPC分类号： H01L21/467 , H01L23/58
CPC分类号： H01L21/0271 , H01L21/0332 , H01L21/3081 , H01L21/32139
摘要： A stacked structure for patterning a material layer to form an opening pattern with a predetermined opening width in the layer is provided. The stacked structure includes an underlayer, a silicon rich organic layer, and a photoresist layer. The underlayer is on the material layer. The silicon rich organic layer is between the underlayer and the photoresist layer. The thickness of the photoresist layer is smaller than that of the underlayer and larger than two times of the thickness of the silicon rich organic layer. The thickness of the underlayer is smaller than three times of the predetermined opening width.
摘要翻译： 提供了用于图案化材料层以形成在该层中具有预定开口宽度的开口图案的层叠结构。 层叠结构包括底层，富硅有机层和光致抗蚀剂层。 底层在材料层上。 富硅有机层位于底层和光刻胶层之间。 光致抗蚀剂层的厚度小于底层的厚度，并且大于富硅有机层的厚度的两倍。 底层的厚度小于预定开口宽度的三倍。
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公开(公告)号：US20080102643A1
公开(公告)日：2008-05-01
申请号：US11554600
申请日：2006-10-31
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31144 , H01L21/28123 , H01L21/3081 , H01L21/3086 , H01L21/31138 , H01L21/32139 , H01L21/76224 , H01L21/76802
摘要： A patterning method is provided. The method includes the steps of firstly forming an underlying layer, a silicon rich organic layer, and a photoresist layer on the material layer in succession. The photoresist layer is patterned, and the silicon rich organic layer is etched using the photoresist layer as a mask. Then, an etching process is performed to pattern the underlying layer using the silicon rich organic layer as a mask. Reactive gases adopted in the etching process include a passivation gas, an etching gas, and a carrier gas. The passivation gas forms a passivation layer at side walls of the patterned underlying layer during the etching process. After that, the material layer is etched using the underlying layer as a mask to form an opening in material layer. Finally, the underlying layer is removed.
摘要翻译： 提供了图案化方法。 该方法包括以下步骤：首先在材料层上依次形成下层，富硅有机层和光致抗蚀剂层。 对光致抗蚀剂层进行图案化，使用光致抗蚀剂层作为掩模蚀刻富硅有机层。 然后，使用富硅有机层作为掩模进行蚀刻工艺以对下层进行图案化。 在蚀刻工艺中采用的反应气体包括钝化气体，蚀刻气体和载气。 钝化气体在蚀刻工艺期间在图案化的下层的侧壁处形成钝化层。 之后，使用下层作为掩模蚀刻材料层，以在材料层中形成开口。 最后，底层被删除。
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公开(公告)号：US20090081817A1
公开(公告)日：2009-03-26
申请号：US11860792
申请日：2007-09-25
申请人： Lung-En Kuo , Jiunn-Hsiung Liao , Min-Chieh Yang
发明人： Lung-En Kuo , Jiunn-Hsiung Liao , Min-Chieh Yang
IPC分类号： H01L21/66
CPC分类号： H01L21/76224 , H01L22/26
摘要： A patterning method is provided. In the patterning method, a film is formed on a substrate and a pre-layer information is measured. Next, an etching process is performed to etch the film. The etching process includes a main etching step, an etching endpoint detection step, an extension etching step and an over etching step. An extension etching time for performing the extension etching step is set within 10 seconds based on a predetermined correlation between an extension etching time and the pre-layer information, so as to achieve a required film profile.
摘要翻译： 提供了图案化方法。 在图案化方法中，在基板上形成膜，并测量预层信息。 接下来，进行蚀刻处理以蚀刻该膜。 蚀刻工艺包括主蚀刻步骤，蚀刻终点检测步骤，延伸蚀刻步骤和过蚀刻步骤。 基于预定的延长蚀刻时间和预层信息之间的相关性，在10秒钟内设定用于进行延长蚀刻步骤的延长蚀刻时间，以便获得所需的膜轮廓。
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公开(公告)号：US07851370B2
公开(公告)日：2010-12-14
申请号：US11860792
申请日：2007-09-25
申请人： Lung-En Kuo , Jiunn-Hsiung Liao , Min-Chieh Yang
发明人： Lung-En Kuo , Jiunn-Hsiung Liao , Min-Chieh Yang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/76224 , H01L22/26
摘要： A patterning method is provided. In the patterning method, a film is formed on a substrate and a pre-layer information is measured. Next, an etching process is performed to etch the film. The etching process includes a main etching step, an etching endpoint detection step, an extension etching step and an over etching step. An extension etching time for performing the extension etching step is set within 10 seconds based on a predetermined correlation between an extension etching time and the pre-layer information, so as to achieve a required film profile.
摘要翻译： 提供了图案化方法。 在图案化方法中，在基板上形成膜，并测量预层信息。 接下来，进行蚀刻处理以蚀刻该膜。 蚀刻工艺包括主蚀刻步骤，蚀刻终点检测步骤，延伸蚀刻步骤和过蚀刻步骤。 基于预定的延长蚀刻时间和预层信息之间的相关性，在10秒钟内设置用于进行延长蚀刻步骤的延长蚀刻时间，以获得所需的膜轮廓。
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10.发明授权公开(公告)号：US08704294B2
公开(公告)日：2014-04-22
申请号：US13158479
申请日：2011-06-13
申请人： Po-Jui Liao , Tsung-Lung Tsai , Chien-Ting Lin , Shao-Hua Hsu , Yeng-Peng Wang , Chun-Hsien Lin , Chan-Lon Yang , Guang-Yaw Hwang , Shin-Chi Chen , Hung-Ling Shih , Jiunn-Hsiung Liao , Chia-Wen Liang
发明人： Po-Jui Liao , Tsung-Lung Tsai , Chien-Ting Lin , Shao-Hua Hsu , Yeng-Peng Wang , Chun-Hsien Lin , Chan-Lon Yang , Guang-Yaw Hwang , Shin-Chi Chen , Hung-Ling Shih , Jiunn-Hsiung Liao , Chia-Wen Liang
IPC分类号： H01L29/66
CPC分类号： H01L29/78 , H01L21/823842 , H01L21/82385 , H01L29/66545
摘要： A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.
摘要翻译： 一种制造具有金属栅极的半导体器件的方法包括：提供具有形成在其上的第一晶体管和第二晶体管的衬底，所述第一晶体管具有形成在其中的第一栅极沟槽，在所述第一栅极沟槽中形成第一功函数金属层， 在第一栅极沟槽中的牺牲掩模层，去除牺牲掩模层的一部分以暴露第一功函数金属层的一部分，去除暴露的第一功能金属层，以在第一栅极沟槽中的第一栅极沟槽中形成U形功函数金属层 栅极沟槽，以及去除牺牲掩模层。 第一晶体管包括第一导电类型，第二晶体管包括第二导电类型。 第一导电类型和第二导电类型是互补的。
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