公开(公告)号：US08943391B2

公开(公告)日：2015-01-27

申请号：US13609829

申请日：2012-09-11

申请人： Yi-Min Lin ,  Chih-Hsiang Hsu ,  Hsie-Chia Chang ,  Chen-Yi Lee

发明人： Yi-Min Lin ,  Chih-Hsiang Hsu ,  Hsie-Chia Chang ,  Chen-Yi Lee

IPC分类号： H03M13/00 ,  H03M13/15 ,  H03M13/45

CPC分类号： H03M13/152 ,  H03M13/1525 ,  H03M13/159 ,  H03M13/451 ,  H03M13/6502

摘要： In a cyclic code decoding method, a decoder analyzes a received codeword to identify unreliable symbols in the codeword, and sets candidate syndrome patterns accordingly. Then, a syndrome calculator calculates evaluated syndrome values associated with one of the candidate syndrome patterns, and an error location polynomial (ELP) generator generates an ELP according to the syndrome values. An error correction device corrects the errors in the codeword according to the ELP when a degree of the ELP is not more than a threshold value, and the syndrome calculator adjusts the syndrome values and the ELP generator generates another ELP according to the adjusted syndrome values when otherwise.

摘要翻译： 在循环码解码方法中，解码器分析接收的码字以识别码字中的不可靠符号，并相应地设置候选综合征模式。 然后，校正子计算器计算与候选校正子模式中的一个相关联的评估校正子值，并且错误位置多项式（ELP）生成器根据校正子值生成ELP。 当ELP的程度不大于阈值时，错误校正装置根据ELP校正码字中的错误，并且校正子计算器调整校正子值，并且ELP生成器根据校正的校正子值生成另一ELP， 除此以外。

公开(公告)号：US20130111304A1

公开(公告)日：2013-05-02

申请号：US13609829

申请日：2012-09-11

申请人： Yi-Min Lin ,  Chih-Hsiang Hsu ,  Hsie-Chia Chang ,  Chen-Yi Lee

发明人： Yi-Min Lin ,  Chih-Hsiang Hsu ,  Hsie-Chia Chang ,  Chen-Yi Lee

IPC分类号： H03M13/07 ,  G06F11/10

CPC分类号： H03M13/152 ,  H03M13/1525 ,  H03M13/159 ,  H03M13/451 ,  H03M13/6502

摘要： In a cyclic code decoding method, a decoder analyzes a received codeword to identify unreliable symbols in the codeword, and sets candidate syndrome patterns accordingly. Then, a syndrome calculator calculates evaluated syndrome values associated with one of the candidate syndrome patterns, and an error location polynomial (ELP) generator generates an ELP according to the syndrome values. An error correction device corrects the errors in the codeword according to theELP when a degree of the ELP is not more than a threshold value, and the syndrome calculator adjusts the syndrome values and the ELP generator generates another ELP according to the adjusted syndrome values when otherwise.

摘要翻译： 在循环码解码方法中，解码器分析接收的码字以识别码字中的不可靠符号，并相应地设置候选综合征模式。 然后，校正子计算器计算与候选校正子模式中的一个相关联的评估校正子值，并且错误位置多项式（ELP）生成器根据校正子值生成ELP。 当ELP的程度不大于阈值时，错误校正装置根据ELP校正码字中的错误，并且校正子计算器调整校正子值，并且ELP生成器根据校正的校正子值生成另一ELP， 除此以外。

公开(公告)号：US08645807B2

公开(公告)日：2014-02-04

申请号：US12790875

申请日：2010-05-31

申请人： Yi-Min Lin ,  Chi-Heng Yang ,  Hsie-Chia Chang ,  Chen-Yi Lee

发明人： Yi-Min Lin ,  Chi-Heng Yang ,  Hsie-Chia Chang ,  Chen-Yi Lee

IPC分类号： H03M13/00

CPC分类号： H03M13/1515 ,  H03M13/152 ,  H03M13/1525 ,  H03M13/1545 ,  H03M13/158 ,  H03M13/6513 ,  H03M13/6516 ,  H03M13/6561

摘要： An apparatus of processing polynomials includes at least one reconfigurable module and an encoder controller. The reconfigurable module includes a plurality of linear feedback shift registers. The encoder controller can control the reconfigurable module to factor a generator polynomial into a factorial polynomial. In the reconfigurable module, the linear feedback shift registers can register a plurality of factors of the factorial polynomial respectively.

摘要翻译： 处理多项式的装置包括至少一个可重新配置模块和编码器控制器。 可重构模块包括多个线性反馈移位寄存器。 编码器控制器可以控制可重构模块将生成多项式归因于阶乘多项式。 在可重构模块中，线性反馈移位寄存器可分别注册多项因子多项式。

公开(公告)号：US07724772B2

公开(公告)日：2010-05-25

申请号：US11802028

申请日：2007-05-18

申请人： Chen-Yi Lee ,  Chih-Hao Liu ,  Chien-Ching Lin ,  Hsie-Chia Chang ,  Yar-Sun Hsu

发明人： Chen-Yi Lee ,  Chih-Hao Liu ,  Chien-Ching Lin ,  Hsie-Chia Chang ,  Yar-Sun Hsu

IPC分类号： H04J3/16

CPC分类号： H04L1/0052 ,  H03M13/116 ,  H03M13/6502 ,  H03M13/6519 ,  H03M13/6527 ,  H03M13/6544 ,  H04L2001/0097

摘要： A method and apparatus for switching data in communication system which comprises of mainly a conversion circuit to receive source data possessing real coding dimension and covert it to converted data possessing tolerable coding dimension; judgment bit is set in the converted data to designate the data as source data or not. Later on, shift circuit is used to shift the converted data in certain amount so as to generate a shifted data; meanwhile, the lowest bit and highest bit of shifted data are used to start acquiring real coding dimension to be used respectively as a first data and a second data, or by changing the pattern of acquiring the first data, then the highest bit minus the real coding dimension bit as the starting bit of the first data, and acquiring the real coding dimension from the side of the lowest bit. Finally, a comparison and selection circuit is used to compare the corresponding judgment bit in the first and the second data and to output an output data, wherein output data is source data with the above-mentioned amount of shift.

摘要翻译： 一种用于在通信系统中切换数据的方法和装置，其主要包括：转换电路，用于接收具有实际编码维度的源数据，并将其转换为具有可容忍编码维度的转换数据; 在转换的数据中设置判断位以将数据指定为源数据。 稍后，使用移位电路将转换后的数据移动到一定量，以产生移位数据; 同时，移位数据的最低位和最高位被用于开始获取要被分别用作第一数据和第二数据的实数编码维度，或通过改变获取第一数据的模式，然后最高位减去实数 编码维度位作为第一数据的起始位，并且从最低位的侧面获取实际编码维度。 最后，比较和选择电路用于比较第一和第二数据中相应的判断位，并输出输出数据，其中输出数据是具有上述移位量的源数据。

公开(公告)号：US07724770B2

公开(公告)日：2010-05-25

申请号：US11708608

申请日：2007-02-21

申请人： Chen-Yi Lee ,  Jr-Hau Lu ,  Chien-Ching Lin ,  Hsie-Chia Chang ,  Yar-Sun Hsu

发明人： Chen-Yi Lee ,  Jr-Hau Lu ,  Chien-Ching Lin ,  Hsie-Chia Chang ,  Yar-Sun Hsu

IPC分类号： H04J3/16

CPC分类号： H04L12/4625

摘要： A method and apparatus for switching data in communication system which comprises of mainly a conversion circuit to receive the source data possessing in a real coding dimension and covert it to converted the data possessing in a tolerable coding dimension; the judgment bits are set in the converted data to designate the data as source data or not. Later on, shifter circuit is used to shift the converted data in certain amount and generates a shifted data; meanwhile, the right side and left side of shifted data are used to start acquiring the real coding dimension to be used respectively as a first data and a second data. Finally, a comparison and selection circuit is used to compare the corresponding judgment bits in the first and the second data and to output an output data, wherein output data is source data with the above-mentioned amount of shift.

摘要翻译： 一种用于在通信系统中切换数据的方法和装置，主要包括一个转换电路，用于接收具有实际编码维度的源数据，并将其转换成可转换的数据，该数据具有可容忍的编码维度; 在转换的数据中设置判断位以将数据指定为源数据。 稍后，使用移位电路将转换的数据移位一定量并产生移位的数据; 同时，使用移位数据的右侧和左侧开始获取要被分别用作第一数据和第二数据的实际编码维度。 最后，比较和选择电路用于比较第一和第二数据中相应的判断位，并输出输出数据，其中输出数据是具有上述移位量的源数据。

公开(公告)号：US20090037799A1

公开(公告)日：2009-02-05

申请号：US11939119

申请日：2007-11-13

申请人： Chih-Hao LIU ,  Yen-Chin Liao ,  Chen-Yi Lee ,  Hsie-Chia Chang ,  Yarsun Hsu

发明人： Chih-Hao LIU ,  Yen-Chin Liao ,  Chen-Yi Lee ,  Hsie-Chia Chang ,  Yarsun Hsu

IPC分类号： H03M13/47 ,  G06F11/00

CPC分类号： H03M13/1137 ,  H03M13/1114 ,  H03M13/658 ,  H03M13/6591

摘要： An operating method applied to low density parity check (LDPC) decoders and the circuit thereof are proposed, in which original bit nodes are incorporated into check nodes for simultaneous operation. The bit node messages are generated according to the different between the newly generated check messages and the previously check node messages. The bit node messages can be updated immediately, and the decoder throughput can be improved. In the other way, the required memory of LDPC decoders can be effectively reduced, and the decoding speed can also be enhanced.

摘要翻译： 提出了一种应用于低密度奇偶校验（LDPC）解码器及其电路的操作方法，其中将原始比特节点并入校验节点以用于同时操作。 根据新生成的检查消息和先前检查节点消息之间的不同，生成位节点消息。 可以立即更新位节点消息，并且可以提高解码器吞吐量。 另一方面，可以有效地减少LDPC解码器所需的存储器，并且也可以提高解码速度。

公开(公告)号：US07724163B2

公开(公告)日：2010-05-25

申请号：US12178987

申请日：2008-07-24

申请人： Cheng-Chi Wong ,  Yung-Yu Lee ,  Ming-Wei Lai ,  Chien-Ching Lin ,  Hsie-Chia Chang ,  Chen-Yi Lee

发明人： Cheng-Chi Wong ,  Yung-Yu Lee ,  Ming-Wei Lai ,  Chien-Ching Lin ,  Hsie-Chia Chang ,  Chen-Yi Lee

IPC分类号： H03M7/00

CPC分类号： H03M13/2775 ,  H03M13/2739 ,  H03M13/2957 ,  H03M13/6566

摘要： An apparatus and method of multi-stage network for iterative network are disclosed. The apparatus has M stages, and each stage uses N multiplexers to transmit N codeword partitions simultaneously. Every starting terminal, either the output port of memories, soft-in soft-out decoders, or multiplexers, has two paths to couple with two different multiplexers at next stage. One path connects the source to the first data port of one multiplexer; the other connects the source to the second data port of another multiplexer. The two multiplexers will be controlled with the same 1-bit signal, so each source has only one valid path to next stage. The invention can guarantee that the transmission of N data blocks is free from contention.

摘要翻译： 公开了一种用于迭代网络的多级网络的装置和方法。 该装置具有M级，每级使用N个多路复用器同时发送N个码字分区。 每个起始终端，存储器的输出端口，软入门解码器或多路复用器都具有两条路径，用于在下一级与两个不同的多路复用器耦合。 一条路径将源连接到一个多路复用器的第一个数据端口; 另一个将源连接到另一个多路复用器的第二个数据端口。 两个多路复用器将以相同的1位信号进行控制，因此每个源只有一条到下一级的有效路径。 本发明可以保证N个数据块的传输没有争用。

公开(公告)号：US20090146849A1

公开(公告)日：2009-06-11

申请号：US12048101

申请日：2008-03-13

申请人： Chih-Hao LIU ,  Chien-Ching Lin ,  Chen-Yi Lee ,  Hsie-Chia Chang ,  Yarsun Hsu

发明人： Chih-Hao LIU ,  Chien-Ching Lin ,  Chen-Yi Lee ,  Hsie-Chia Chang ,  Yarsun Hsu

IPC分类号： H03M7/00

CPC分类号： H03M13/116 ,  H03M13/1105 ,  H03M13/1111 ,  H03M13/6561

摘要： A multi-mode multi-parallelism data exchange method and the device thereof are proposed to apply to a check node operator or a bit node operator. The proposed method comprises the steps of: duplicating part or all of an original shift data as a duplicated shift data; combining the original shift data and the duplicated shift data to form a data block; and using a data block as the unit to shift this data block so as to conveniently retrieve shift data from the shifted data block. With a maximum z factor circuit and duplication of part of data, specifications of different shift sizes can be supported. The functions of shifters of several sizes can therefore be accomplished with the minimum complexity.

摘要翻译： 提出了一种多模式多并行数据交换方法及其装置，以应用于校验节点运算符或位节点运算符。 所提出的方法包括以下步骤：将原始移位数据的一部分或全部复制为复制移位数据; 组合原始移位数据和复制的移位数据以形成数据块; 并且使用数据块作为单元来移位该数据块，从而便于从移位的数据块检索移位数据。 通过最大的z因子电路和部分数据的重复，可以支持不同位移大小的规范。 因此可以以最小的复杂度来实现几种尺寸的移位器的功能。

公开(公告)号：US06954892B2

公开(公告)日：2005-10-11

申请号：US10162911

申请日：2002-06-06

申请人： Chen-Yi Lee ,  Hsie-Chia Chang ,  Chien-Ching Lin

发明人： Chen-Yi Lee ,  Hsie-Chia Chang ,  Chien-Ching Lin

IPC分类号： H03M13/15 ,  H03M13/00

CPC分类号： H03M13/159 ,  H03M13/151

摘要： The present invention provides a method of calculating the syndrome polynomial in decoding error correction codes. From the relation between the syndromes and the coefficients of the error locator polynomial, the inference that the first t syndromes are zeros, then the next t syndromes are also zeros can be deduced, wherein t is the largest number of correctable errors. For all received codewords, the first t syndromes are calculated. Next, whether the first t syndromes are zeros is judged. If the first t syndromes are zeros, the computation is stopped; otherwise, the next t syndromes are calculated. Therefore, the present invention can judge whether the received codeword is erroneous with only a half of computation, hence effectively reducing the computation in practical operation and achieving the object of low power consumption.

摘要翻译： 本发明提供了一种在解码纠错码中计算校正子多项式的方法。 从综合征与误差定位多项式的系数之间的关系，推导出第一个t综合征为零，则下一个t个综合征也可以是零，其中t是可纠正错误的最大数目。 对于所有接收到的码字，计算第一个t综合征。 接下来，判断第一个t综合征是否为零。 如果第一个t综合征为零，计算停止; 否则，计算下一个t综合征。 因此，本发明可以仅用计算的一半来判断接收到的代码字是否是错误的，从而有效地减少了实际操作中的计算，并实现了低功耗的目的。

公开(公告)号：US08108762B2

公开(公告)日：2012-01-31

申请号：US11939119

申请日：2007-11-13

申请人： Chih-Hao Liu ,  Yen-Chin Liao ,  Chen-Yi Lee ,  Hsie-Chia Chang ,  Yarsun Hsu

发明人： Chih-Hao Liu ,  Yen-Chin Liao ,  Chen-Yi Lee ,  Hsie-Chia Chang ,  Yarsun Hsu

IPC分类号： G06F11/00 ,  H03M13/00

CPC分类号： H03M13/1137 ,  H03M13/1114 ,  H03M13/658 ,  H03M13/6591

摘要： An operating method and a circuit for low density parity check (LDPC) decoders, in which original bit nodes are incorporated into check nodes for simultaneous operation. The bit node messages are generated according to the difference between the newly generated check messages and the previous check node messages. The bit node messages can be updated immediately, and the decoder throughput can be improved. The required memory of LDPC decoders can be effectively reduced, and the decoding speed can also be enhanced.

摘要翻译： 一种用于低密度奇偶校验（LDPC）解码器的操作方法和电路，其中将原始比特节点并入校验节点用于同时操作。 根据新生成的检查消息和先前检查节点消息之间的差异来生成位节点消息。 可以立即更新位节点消息，并且可以提高解码器吞吐量。 可以有效地减少LDPC解码器所需的存储器，并且还可以提高解码速度。