公开(公告)号：US20080290380A1

公开(公告)日：2008-11-27

申请号：US11753374

申请日：2007-05-24

申请人： Yi-Ming Sheu ,  Da-Wen Lin ,  Shyh-Wei Wang

发明人： Yi-Ming Sheu ,  Da-Wen Lin ,  Shyh-Wei Wang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7843 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes a substrate and a gate formed on the substrate. A gate spacer is formed next to the gate. The gate spacer has a height greater than the height of the gate. A method of forming a semiconductor device includes providing a substrate with a gate layer. A hard mask layer is formed over the gate layer, and both layers are then etched using a pattern, forming a gate and a hard mask. A spacer layer is then deposited over the substrate, gate, and hard mask. The spacer layer is etched to form a gate spacer next to the gate. The hard mask is then removed.

摘要翻译： 半导体器件包括衬底和形成在衬底上的栅极。 在栅极旁边形成栅极间隔物。 栅极间隔物的高度大于栅极的高度。 形成半导体器件的方法包括：提供具有栅极层的衬底。 在栅极层上形成硬掩模层，然后使用图案蚀刻两层，形成栅极和硬掩模。 然后将间隔层沉积在衬底，栅极和硬掩模上。 蚀刻间隔层以在栅极附近形成栅极间隔。 然后去除硬面罩。

公开(公告)号：US20050127433A1

公开(公告)日：2005-06-16

申请号：US10728967

申请日：2003-12-04

申请人： Da-Wen Lin ,  Yi-Ming Sheu ,  Ying-Keung Leung

发明人： Da-Wen Lin ,  Yi-Ming Sheu ,  Ying-Keung Leung

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/66553 ,  H01L29/42368 ,  H01L29/665 ,  H01L29/66621 ,  H01L29/7834

摘要： A gate structure and method for forming the same the method including providing a silicon substrate including one of N and P-well doped regions and an overlying the CVD silicon oxide layer; forming an opening in the CVD silicon oxide layer to include a recessed area extending into a thickness portion of the silicon substrate; thermally growing a gate oxide over exposed silicon substrate portions of the recessed area; backfilling the opening with polysilicon; planarizing the polysilicon to the opening level to reveal the silicon oxide layer; and, selectively removing the silicon oxide layer to form a recessed gate structure.

摘要翻译： 一种用于形成该方法的栅极结构和方法，包括提供包括N阱和P阱掺杂区域之一的硅衬底以及覆盖所述CVD氧化硅层的方法; 在所述CVD氧化硅层中形成开口以包括延伸到所述硅衬底的厚度部分的凹陷区域; 在凹陷区域的暴露的硅衬底部分上热生长栅极氧化物; 用多晶硅回填开口; 将多晶硅平坦化至开口水平以显示氧化硅层; 并且选择性地去除氧化硅层以形成凹陷栅极结构。

公开(公告)号：US07399679B2

公开(公告)日：2008-07-15

申请号：US11288858

申请日：2005-11-29

申请人： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

发明人： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

IPC分类号： H01L21/337 ,  H01L21/336 ,  H01L21/76 ,  H01L21/425

CPC分类号： H01L28/40 ,  H01L21/31144 ,  H01L21/76237 ,  H01L21/823481 ,  H01L27/10835 ,  H01L27/10861 ,  H01L27/1087

摘要： A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

摘要翻译： 描述了一种在NMOS晶体管中减小反向窄宽度效应的方法。 氧化物衬垫沉积在形成为隔离衬底中的有源区域的浅沟槽中。 在浅沟槽中形成光致抗蚀剂插塞，并且在衬底的顶部下方凹入以暴露氧化物衬垫的顶部部分。 然后进行通过氧化物衬垫到衬底中的成角度的铟植入物。 去除插头并沉积绝缘体以填充沟槽。 在平坦化和湿蚀刻步骤之后，形成栅极介电层和图案化栅极层，NMOS晶体管对于长沟道和短沟道都表现出改善的Vt滚降为40至45毫伏。 在不会降低结或隔离性能的情况下实现改进。 可以改变铟注入剂量和角度以提供该过程的灵活性。

公开(公告)号：US07012014B2

公开(公告)日：2006-03-14

申请号：US10728967

申请日：2003-12-04

申请人： Da-Wen Lin ,  Yi-Ming Sheu ,  Ying-Keung Leung

发明人： Da-Wen Lin ,  Yi-Ming Sheu ,  Ying-Keung Leung

IPC分类号： H01L21/3205

CPC分类号： H01L29/66553 ,  H01L29/42368 ,  H01L29/665 ,  H01L29/66621 ,  H01L29/7834

摘要： A gate structure and method for forming the same the method including providing a silicon substrate including one of N and P-well doped regions and an overlying the CVD silicon oxide layer; forming an opening in the CVD silicon oxide layer to include a recessed area extending into a thickness portion of the silicon substrate; thermally growing a gate oxide over exposed silicon substrate portions of the recessed area; backfilling the opening with polysilicon; planarizing the polysilicon to the opening level to reveal the silicon oxide layer; and, selectively removing the silicon oxide layer to form a recessed gate structure.

摘要翻译： 一种用于形成该方法的栅极结构和方法，包括提供包括N阱和P阱掺杂区域之一的硅衬底以及覆盖所述CVD氧化硅层的方法; 在所述CVD氧化硅层中形成开口以包括延伸到所述硅衬底的厚度部分的凹陷区域; 在凹陷区域的暴露的硅衬底部分上热生长栅极氧化物; 用多晶硅回填开口; 将多晶硅平坦化至开口水平以显示氧化硅层; 并且选择性地去除氧化硅层以形成凹陷栅极结构。

公开(公告)号：US07071515B2

公开(公告)日：2006-07-04

申请号：US10619114

申请日：2003-07-14

申请人： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

发明人： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/823481 ,  H01L21/26586 ,  H01L21/76237

摘要： A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

摘要翻译： 描述了一种在NMOS晶体管中减小反向窄宽度效应的方法。 氧化物衬垫沉积在形成为隔离衬底中的有源区域的浅沟槽中。 在浅沟槽中形成光致抗蚀剂插塞，并且在衬底的顶部下方凹入以暴露氧化物衬垫的顶部部分。 然后进行通过氧化物衬垫到衬底中的成角度的铟植入物。 去除插头并沉积绝缘体以填充沟槽。 在平坦化和湿蚀刻步骤之后，形成栅极介电层和图案化栅极层，NMOS晶体管对于长沟道和短沟道都表现出改善的Vt滚降为40至45毫伏。 在不会降低结或隔离性能的情况下实现改进。 可以改变铟注入剂量和角度以提供该过程的灵活性。

公开(公告)号：US06673683B1

公开(公告)日：2004-01-06

申请号：US10291029

申请日：2002-11-07

申请人： Yi-Ming Sheu ,  Yi-Ling Chan ,  Da-Wen Lin ,  Wan-Yih Lien ,  Carlos H. Diaz

发明人： Yi-Ming Sheu ,  Yi-Ling Chan ,  Da-Wen Lin ,  Wan-Yih Lien ,  Carlos H. Diaz

IPC分类号： H01L21336

CPC分类号： H01L29/66553 ,  H01L29/66545 ,  H01L29/6659

摘要： A method for forming a field effect transistor device within a semiconductor product employs a patterned dummy layer first as an ion implantation mask layer when forming a pair of source/drain regions, and then as a mandrel layer for forming a pair of patterned sacrificial layers which define an aperture of linewidth and location corresponding to the patterned dummy layer. A pair of sacrificial spacer layers and a gate electrode are then formed self-aligned within the aperture. The pair of patterned sacrificial layers and the pair of sacrificial spacer layers are then stripped and the gate electrode is employed as a mask for ion implanting forming a pair of lightly doped extension regions partially overlapping the pair of source/drain regions within the semiconductor substrate.

摘要翻译： 在半导体产品中形成场效应晶体管器件的方法当形成一对源极/漏极区域时首先使用图案化虚拟层作为离子注入掩模层，然后作为用于形成一对图案化牺牲层的心轴层， 限定对应于图案化虚拟层的线宽和位置的孔径。 然后在孔内自对准地形成一对牺牲间隔层和栅电极。 然后剥去一对图案化牺牲层和一对牺牲隔离层，并且使用栅电极作为用于离子注入的掩模，形成与半导体衬底内的一对源/漏区部分重叠的一对轻掺杂的延伸区。

公开(公告)号：US06670226B2

公开(公告)日：2003-12-30

申请号：US10094460

申请日：2002-03-08

申请人： Yo-Sheng Lin ,  Yi-Ming Sheu ,  Da-Wen Lin ,  Chi-Hsun Hsieh

发明人： Yo-Sheng Lin ,  Yi-Ming Sheu ,  Da-Wen Lin ,  Chi-Hsun Hsieh

IPC分类号： H01L218238

CPC分类号： H01L21/823842 ,  H01L21/32115 ,  H01L21/3212

摘要： Within a method for fabricating a semiconductor integrated circuit microelectronic fabrication, there is employed a planarizing method for forming, in a self aligned fashion, a patterned second gate electrode material layer laterally adjacent but not over a patterned first gate electrode material layer, such that upon further patterning of the patterned first gate electrode material layer and the patterned second gate electrode material layer there may be formed a first gate electrode over a first active region of a semiconductor substrate and a second gate electrode over a laterally adjacent second active region of the semiconductor substrate. The method is particularly useful within the context of complementary metal oxide semiconductor (CMOS) semiconductor integrated circuit microelectronic fabrications.

公开(公告)号：US20060079068A1

公开(公告)日：2006-04-13

申请号：US11288858

申请日：2005-11-29

申请人： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

发明人： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

IPC分类号： H01L21/76

CPC分类号： H01L28/40 ,  H01L21/31144 ,  H01L21/76237 ,  H01L21/823481 ,  H01L27/10835 ,  H01L27/10861 ,  H01L27/1087

摘要： A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

公开(公告)号：US20050012173A1

公开(公告)日：2005-01-20

申请号：US10619114

申请日：2003-07-14

申请人： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

发明人： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

IPC分类号： H01L21/762 ,  H01L21/8234 ,  H01L21/76 ,  H01L21/337 ,  H01L29/00

CPC分类号： H01L21/823481 ,  H01L21/26586 ,  H01L21/76237

摘要： A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

摘要翻译： 描述了一种在NMOS晶体管中减小反向窄宽度效应的方法。 氧化物衬垫沉积在形成为隔离衬底中的有源区域的浅沟槽中。 在浅沟槽中形成光致抗蚀剂插塞，并且在衬底的顶部下方凹入以暴露氧化物衬垫的顶部部分。 然后进行通过氧化物衬垫到衬底中的成角度的铟植入物。 去除插头并沉积绝缘体以填充沟槽。 在平坦化和湿蚀刻步骤之后，形成栅极介电层和图案化栅极层，NMOS晶体管对于长沟道和短沟道都表现出改善的Vt滚降为40至45毫伏。 在不会降低结或隔离性能的情况下实现改进。 可以改变铟注入剂量和角度以提供该过程的灵活性。

公开(公告)号：US08354718B2

公开(公告)日：2013-01-15

申请号：US11751959

申请日：2007-05-22

申请人： Chih-Chiang Wang ,  Yi-Ming Sheu ,  Ying-Shiou Lin

发明人： Chih-Chiang Wang ,  Yi-Ming Sheu ,  Ying-Shiou Lin

IPC分类号： H01L21/02

CPC分类号： H01L29/1083 ,  H01L29/66636

摘要： An apparatus comprising a substrate of first dopant type and first dopant concentration; pocket regions in the substrate and having the first dopant type and a second dopant concentration greater than the first dopant concentration; a gate stack over the substrate and laterally between the pocket regions; first and second source/drain regions on opposing sides of the gate stack and vertically between the gate stack and the pocket regions, the first and second source/drain regions having a second dopant type opposite the first dopant type and a third dopant concentration; and third and fourth source/drain regions having the second dopant type and a fourth dopant concentration that is greater than the third dopant concentration, wherein the pocket regions are between the third and fourth source/drain regions, and the third and fourth source/drain regions are vertically between the first and second source/drain regions and a bulk portion of the substrate.

摘要翻译： 一种装置，包括第一掺杂剂型和第一掺杂剂浓度的衬底; 并且具有大于第一掺杂剂浓度的第一掺杂剂类型和第二掺杂剂浓度; 在所述衬底上方的栅堆叠，并且在所述袋区域之间横向; 第一和第二源极/漏极区域在栅极堆叠的相对侧上并且垂直地在栅极堆叠层与凹穴区域之间，第一和第二源极/漏极区域具有与第一掺杂剂类型相反的第二掺杂剂类型和第三掺杂剂浓度; 以及具有大于第三掺杂剂浓度的第二掺杂剂类型和第四掺杂剂浓度的第三和第四源极/漏极区域，其中所述穴状区域在第三和第四源极/漏极区域之间，并且第三和第四源极/漏极 区域在第一和第二源极/漏极区域之间以及基板的主体部分之间是垂直的。