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公开(公告)号：US20070035026A1
公开(公告)日：2007-02-15
申请号：US11203237
申请日：2005-08-15
申请人： Yi-Nien Su , Jyu-Horng Shieh , Cheng-Lin Huang , Jing-Cheng Lin , Ching-Hua Hsieh , Shau-Lin Shue
发明人： Yi-Nien Su , Jyu-Horng Shieh , Cheng-Lin Huang , Jing-Cheng Lin , Ching-Hua Hsieh , Shau-Lin Shue
CPC分类号： H01L21/76804 , H01L21/76805 , H01L21/76816 , H01L21/76847 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： An opening in a semiconductor device with improved step coverage. The opening comprises a dielectric layer overlying a substrate, having at least one via opening to expose the substrate. The via opening comprises a step region in the upper portion of the via opening and a concave profile region with respect to the dielectric layer in the lower portion of the via opening. A semiconductor device with the opening is also disclosed.
摘要翻译： 半导体器件的开口，具有改进的台阶覆盖。 开口包括覆盖衬底的电介质层，具有至少一个通孔以暴露衬底。 通孔开口包括在通孔开口的上部中的台阶区域和相对于通孔开口下部的电介质层的凹形轮廓区域。 还公开了一种具有开口的半导体器件。
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公开(公告)号：US20060027922A1
公开(公告)日：2006-02-09
申请号：US10909980
申请日：2004-08-03
申请人： Hsien-Ming Lee , Jing-Cheng Lin , Shing-Chyang Pan , Ching-Hua Hsieh , Chao-Hsien Peng , Cheng-Lin Huang , Li-Lin Su , Shau-Lin Shue
发明人： Hsien-Ming Lee , Jing-Cheng Lin , Shing-Chyang Pan , Ching-Hua Hsieh , Chao-Hsien Peng , Cheng-Lin Huang , Li-Lin Su , Shau-Lin Shue
IPC分类号： H01L23/48
CPC分类号： H01L21/76834 , H01L21/76849 , H01L21/76867 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a nonconductive cap layer comprising a first metal element. The nonconductive cap layer comprises a first metal nitride, a first metal oxide, or a first metal oxynitride over conductive lines and an insulating material between the conductive lines. An interface region may be formed over the top surface of the conductive lines, the interface region including the metal element of the cap layer. The cap layer prevents the conductive material in the conductive lines from migrating or diffusing into adjacent subsequently formed insulating material layers. The cap layer may also function as an etch stop layer.
摘要翻译： 一种具有包括第一金属元件的非导电盖层的半导体器件。 非导电盖层包括导电线上的第一金属氮化物，第一金属氧化物或第一金属氧氮化物，以及导电线之间的绝缘材料。 界面区域可以形成在导电线的顶表面上，界面区域包括盖层的金属元件。 盖层防止导电线中的导电材料迁移或扩散到相邻的随后形成的绝缘材料层中。 盖层也可以用作蚀刻停止层。
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公开(公告)号：US20050054202A1
公开(公告)日：2005-03-10
申请号：US10655972
申请日：2003-09-04
申请人： Shing-Chyang Pan , Ching-Hua Hsieh , Jing-Cheng Lin , Hsien-Ming Lee , Cheng-Lin Huang , Shau-Lin Shue
发明人： Shing-Chyang Pan , Ching-Hua Hsieh , Jing-Cheng Lin , Hsien-Ming Lee , Cheng-Lin Huang , Shau-Lin Shue
IPC分类号： H01L21/285 , H01L21/3105 , H01L21/311 , H01L21/768
CPC分类号： H01L21/3105 , H01L21/28556 , H01L21/76807 , H01L21/76814 , H01L21/76838 , H01L21/76843 , H01L21/76873
摘要： A method for forming a copper damascene feature including providing a semiconductor process wafer including at least one via opening formed to extend through a thickness of at least one dielectric insulating layer and an overlying trench line opening encompassing the at least one via opening to form a dual damascene opening; etching through an etch stop layer at the at least one via opening bottom portion to expose an underlying copper area; carrying out a sub-atmospheric DEGAS process with simultaneous heating of the process wafer in a hydrogen containing ambient; carrying out an in-situ sputter-clean process; and, forming a barrier layer in-situ to line the dual damascene opening.
摘要翻译： 一种用于形成铜镶嵌特征的方法，包括提供半导体工艺晶片，其包括形成为延伸穿过至少一个介电绝缘层的厚度的至少一个通孔开口，以及覆盖所述至少一个通孔开口的上覆沟槽开口，以形成双重 大马士革开幕 在所述至少一个通孔开口底部处蚀刻通过蚀刻停止层以暴露下面的铜区域; 在含氢环境中同时加热工艺晶片，进行亚低温DEGAS工艺; 进行原位溅射清洗过程; 并且原位形成阻挡层以使双镶嵌开口成线。
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公开(公告)号：US20050029665A1
公开(公告)日：2005-02-10
申请号：US10936922
申请日：2004-09-08
IPC分类号： H01L21/31 , H01L21/3205 , H01L21/3213 , H01L21/44 , H01L21/4763 , H01L21/768 , H01L23/52 , H01L23/532
CPC分类号： H01L21/76843 , H01L21/32051 , H01L21/32136 , H01L21/76844 , H01L21/76846 , H01L21/76855 , H01L21/76877 , H01L21/76888 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A new method is provided for the creation of a barrier-free copper interconnect. A dual damascene structure is created in a layer of dielectric, a thin metal barrier layer is deposited. The metal barrier layer is oxidized, two layers are then deposited with the first layer comprising doped copper and the second layer comprising pure copper. The dual damascene structure is filled with copper, a thermal anneal is applied, stabilizing the deposited copper filling the dual damascene structure and forming metal oxide of the doped minority element. Excess copper is then removed from the dielectric.
摘要翻译： 提供了一种创建无障碍铜互连的新方法。 在电介质层中形成双镶嵌结构，沉积薄金属阻挡层。 金属阻挡层被氧化，然后沉积两层，第一层包含掺杂的铜，第二层包含纯铜。 双镶嵌结构填充铜，进行热退火，稳定沉积的铜填充双镶嵌结构并形成掺杂少数元素的金属氧化物。 然后从电介质中除去过量的铜。
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公开(公告)号：US06806192B2
公开(公告)日：2004-10-19
申请号：US10350837
申请日：2003-01-24
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/32051 , H01L21/32136 , H01L21/76844 , H01L21/76846 , H01L21/76855 , H01L21/76877 , H01L21/76888 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A new method is provided for the creation of a barrier-free copper interconnect. A dual damascene structure is created in a layer of dielectric, a thin metal barrier layer is deposited. The metal barrier layer is oxidized, two layers are then deposited with the first layer comprising doped copper and the second layer comprising pure copper. The dual damascene structure is filled with copper, a thermal anneal is applied, stabilizing the deposited copper filling the dual damascene structure and forming metal oxide of the doped minority element. Excess copper is then removed from the dielectric.
摘要翻译： 提供了一种创建无障碍铜互连的新方法。 在电介质层中形成双镶嵌结构，沉积薄金属阻挡层。 金属阻挡层被氧化，然后沉积两层，第一层包含掺杂的铜，第二层包含纯铜。 双镶嵌结构填充铜，进行热退火，稳定沉积的铜填充双镶嵌结构并形成掺杂少数元素的金属氧化物。 然后从电介质中除去过量的铜。
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公开(公告)号：US07215024B2
公开(公告)日：2007-05-08
申请号：US10936922
申请日：2004-09-08
IPC分类号： H01L23/48
CPC分类号： H01L21/76843 , H01L21/32051 , H01L21/32136 , H01L21/76844 , H01L21/76846 , H01L21/76855 , H01L21/76877 , H01L21/76888 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A new method is provided for the creation of a barrier-free copper interconnect. A dual damascene structure is created in a layer of dielectric, a thin metal barrier layer is deposited. The metal barrier layer is oxidized, two layers are then deposited with the first layer comprising doped copper and the second layer comprising pure copper. The dual damascene structure is filled with copper, a thermal anneal is applied, stabilizing the deposited copper filling the dual damascene structure and forming metal oxide of the doped minority element. Excess copper is then removed from the dielectric.
摘要翻译： 提供了一种创建无障碍铜互连的新方法。 在电介质层中形成双镶嵌结构，沉积薄金属阻挡层。 金属阻挡层被氧化，然后沉积两层，第一层包含掺杂的铜，第二层包含纯铜。 双镶嵌结构填充铜，进行热退火，稳定沉积的铜填充双镶嵌结构并形成掺杂少数元素的金属氧化物。 然后从电介质中除去过量的铜。
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公开(公告)号：US07030023B2
公开(公告)日：2006-04-18
申请号：US10655972
申请日：2003-09-04
申请人： Shing-Chyang Pan , Ching-Hua Hsieh , Jing-Cheng Lin , Hsien-Ming Lee , Cheng-Lin Huang , Shau-Lin Shue
发明人： Shing-Chyang Pan , Ching-Hua Hsieh , Jing-Cheng Lin , Hsien-Ming Lee , Cheng-Lin Huang , Shau-Lin Shue
IPC分类号： H01L21/302
CPC分类号： H01L21/3105 , H01L21/28556 , H01L21/76807 , H01L21/76814 , H01L21/76838 , H01L21/76843 , H01L21/76873
摘要： A method for forming a copper damascene feature including providing a semiconductor process wafer including at least one via opening formed to extend through a thickness of at least one dielectric insulating layer and an overlying trench line opening encompassing the at least one via opening to form a dual damascene opening; etching through an etch stop layer at the at least one via opening bottom portion to expose an underlying copper area; carrying out a sub-atmospheric DEGAS process with simultaneous heating of the process wafer in a hydrogen containing ambient; carrying out an in-situ sputter-clean process; and, forming a barrier layer in-situ to line the dual damascene opening.
摘要翻译： 一种用于形成铜镶嵌特征的方法，包括提供半导体工艺晶片，其包括形成为延伸穿过至少一个介电绝缘层的厚度的至少一个通孔开口，以及覆盖所述至少一个通孔开口的上覆沟槽开口，以形成双重 大马士革开幕 在所述至少一个通孔开口底部处蚀刻通过蚀刻停止层以暴露下面的铜区域; 在含氢环境中同时加热工艺晶片，进行亚低温DEGAS工艺; 进行原位溅射清洗过程; 并且原位形成阻挡层以使双镶嵌开口成线。
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公开(公告)号：US20050189075A1
公开(公告)日：2005-09-01
申请号：US10789660
申请日：2004-02-27
申请人： Shing-Chyang Pan , Jing-Cheng Lin , Hsien-Ming Lee , Cheng-Lin Huang , Ching-Hua Hsieh , Chao-Hsien Peng , Li-Lin Su , Shau-Lin Shue
发明人： Shing-Chyang Pan , Jing-Cheng Lin , Hsien-Ming Lee , Cheng-Lin Huang , Ching-Hua Hsieh , Chao-Hsien Peng , Li-Lin Su , Shau-Lin Shue
CPC分类号： H01L21/67109 , B08B7/0071 , H01J37/32862
摘要： A reactive pre-clean chamber that contains a wafer heating apparatus, such as a high-temperature electrostatic chuck (HTESC), for directly heating a wafer supported on the apparatus during a pre-cleaning process. The wafer heating apparatus is capable of heating the wafer to the optimum temperatures required for a hydrogen plasma reactive pre-clean (RPC) process. Furthermore, degassing and pre-cleaning can be carried out in the same pre-clean chamber. The invention further includes a method of pre-cleaning a wafer using a pre-clean chamber that contains a wafer heating apparatus.
摘要翻译： 一种反应性预清洁室，其包含诸如高温静电卡盘（HTESC）的晶片加热装置，用于在预清洁过程期间直接加热支撑在装置上的晶片。 晶片加热装置能够将晶片加热到氢等离子体反应性预清洁（RPC）工艺所需的最佳温度。 此外，脱气和预清洁可以在相同的预清洁室中进行。 本发明还包括使用包含晶片加热装置的预清洁室预清洁晶片的方法。
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公开(公告)号：US07253501B2
公开(公告)日：2007-08-07
申请号：US10909980
申请日：2004-08-03
申请人： Hsien-Ming Lee , Jing-Cheng Lin , Shing-Chyang Pan , Ching-Hua Hsieh , Chao-Hsien Peng , Cheng-Lin Huang , Li-Lin Su , Shau-Lin Shue
发明人： Hsien-Ming Lee , Jing-Cheng Lin , Shing-Chyang Pan , Ching-Hua Hsieh , Chao-Hsien Peng , Cheng-Lin Huang , Li-Lin Su , Shau-Lin Shue
CPC分类号： H01L21/76834 , H01L21/76849 , H01L21/76867 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a nonconductive cap layer comprising a first metal element. The nonconductive cap layer comprises a first metal nitride, a first metal oxide, or a first metal oxynitride over conductive lines and an insulating material between the conductive lines. An interface region may be formed over the top surface of the conductive lines, the interface region including the metal element of the cap layer. The cap layer prevents the conductive material in the conductive lines from migrating or diffusing into adjacent subsequently formed insulating material layers. The cap layer may also function as an etch stop layer.
摘要翻译： 一种具有包括第一金属元件的非导电盖层的半导体器件。 非导电盖层包括导电线上的第一金属氮化物，第一金属氧化物或第一金属氧氮化物，以及导电线之间的绝缘材料。 界面区域可以形成在导电线的顶表面上，界面区域包括盖层的金属元件。 盖层防止导电线中的导电材料迁移或扩散到相邻的随后形成的绝缘材料层中。 盖层也可以用作蚀刻停止层。
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公开(公告)号：US07193327B2
公开(公告)日：2007-03-20
申请号：US11042396
申请日：2005-01-25
申请人： Chen-Hua Yu , Shing-Chyang Pan , Shau-Lin Shue , Ching-Hua Hsieh , Cheng-Lin Huang , Hsien-Ming Lee , Jing-Cheng Lin
发明人： Chen-Hua Yu , Shing-Chyang Pan , Shau-Lin Shue , Ching-Hua Hsieh , Cheng-Lin Huang , Hsien-Ming Lee , Jing-Cheng Lin
CPC分类号： H01L23/53295 , H01L21/76805 , H01L21/76844 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An opening in a dielectric layer having a unique barrier layer structure is provided. In an embodiment, the opening is a via and a trench. The barrier layer, which may comprise one or more barrier layers, is formed such that the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the trench is greater than about 0.55. In another embodiment, the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the via is greater than about 1.0. An underlying conductive layer may be recessed.
摘要翻译： 提供具有独特的阻挡层结构的电介质层中的开口。 在一个实施例中，开口是通孔和沟槽。 可以形成阻挡层，其可以包括一个或多个阻挡层，使得阻挡层的厚度在沟槽的底部和电介质层的顶部之间的大致中间的侧壁与屏障的厚度之比 沿着沟槽底部的层大于约0.55。 在另一个实施例中，沿着沟槽底部和电介质层的顶部之间大约中间的侧壁的阻挡层的厚度与通孔底部的阻挡层的厚度之比大于约1.0。 潜在的导电层可以凹入。
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