公开(公告)号：US20050121716A1

公开(公告)日：2005-06-09

申请号：US10726508

申请日：2003-12-04

Applicant: Wiley Hill ,  Haihong Wang ,  Yider Wu ,  Bin Yu

Inventor： Wiley Hill ,  Haihong Wang ,  Yider Wu ,  Bin Yu

IPC: G11C16/04 ,  H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/785

Abstract: A memory device includes a conductive structure, a number of dielectric layers and a control gate. The dielectric layers are formed around the conductive structure and the control gate is formed over the dielectric layers. A portion of the conductive structure functions as a drain region for the memory device and at least one of the dielectric layers functions as a charge storage structure for the memory device. The dielectric layers may include oxide-nitride-oxide layers.

Abstract translation: 存储器件包括导电结构，多个电介质层和控制栅极。 电介质层形成在导电结构周围，并且控制栅极形成在电介质层上。 导电结构的一部分用作存储器件的漏极区，并且至少一个介电层用作存储器件的电荷存储结构。 电介质层可以包括氧化物 - 氮化物 - 氧化物层。

公开(公告)号：US06963104B2

公开(公告)日：2005-11-08

申请号：US10459576

申请日：2003-06-12

Applicant: Yider Wu ,  Bin Yu

Inventor： Yider Wu ,  Bin Yu

IPC: H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/12 ,  H01L29/786 ,  H01L29/792 ,  H01L29/788

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

Abstract: A non-volatile memory device includes a substrate, an insulating layer, a fin, a number of dielectric layers and a control gate. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The dielectric layers are formed over the fin and the control gate is formed over the dielectric layers. The dielectric layers may include oxide-nitride-oxide layers that function as a charge storage structure for the memory device.

Abstract translation: 非易失性存储器件包括衬底，绝缘层，鳍片，多个电介质层和控制栅极。 绝缘层形成在基板上，并且鳍形成在绝缘层上。 电介质层形成在鳍片之上，并且控制栅极形成在电介质层上。 电介质层可以包括用作存储器件的电荷存储结构的氧化物 - 氮化物 - 氧化物层。

公开(公告)号：US06958512B1

公开(公告)日：2005-10-25

申请号：US10770010

申请日：2004-02-03

Applicant: Yider Wu ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Yider Wu ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L29/788

CPC classification number: H01L29/42324 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7881

Abstract: A non-volatile memory device includes a substrate, an insulating layer, a fin, a conductive structure and a control gate. The insulating layer may be formed on the substrate and the fin may be formed on the insulating layer. The conductive structure may be formed near a side of the fin and the control gate may be formed over the fin. The conductive structure may act as a floating gate electrode for the non-volatile memory device.

Abstract translation: 非易失性存储器件包括衬底，绝缘层，鳍，导电结构和控制栅。 绝缘层可以形成在基板上，并且鳍可以形成在绝缘层上。 导电结构可以形成在鳍的一侧附近，并且控制栅可以形成在翅片上。 导电结构可以用作非易失性存储器件的浮栅电极。

公开(公告)号：US06933558B2

公开(公告)日：2005-08-23

申请号：US10726508

申请日：2003-12-04

Applicant: Wiley Eugene Hill ,  Haihong Wang ,  Yider Wu ,  Bin Yu

Inventor： Wiley Eugene Hill ,  Haihong Wang ,  Yider Wu ,  Bin Yu

IPC: G11C16/04 ,  H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/792

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/785

Abstract: A memory device includes a conductive structure, a number of dielectric layers and a control gate. The dielectric layers are formed around the conductive structure and the control gate is formed over the dielectric layers. A portion of the conductive structure functions as a drain region for the memory device and at least one of the dielectric layers functions as a charge storage structure for the memory device. The dielectric layers may include oxide-nitride-oxide layers.

Abstract translation: 存储器件包括导电结构，多个电介质层和控制栅极。 电介质层形成在导电结构周围，并且控制栅极形成在电介质层上。 导电结构的一部分用作存储器件的漏极区，并且至少一个介电层用作存储器件的电荷存储结构。 电介质层可以包括氧化物 - 氮化物 - 氧化物层。

公开(公告)号：US10297607B2

公开(公告)日：2019-05-21

申请号：US13615723

申请日：2012-09-14

Applicant: Takao Akaogi ,  Yider Wu ,  Yi-Hsiu Chen

Inventor： Takao Akaogi ,  Yider Wu ,  Yi-Hsiu Chen

IPC: H01L27/11565 ,  H01L21/762 ,  H01L27/11568 ,  H01L21/8234

Abstract: A non-volatile memory having discrete isolation structures and SONOS (Silicon Oxide Nitride Oxide Silicon) memory cells, a method of operating the same, and a method of manufacturing the same are introduced. Every isolation structure on a semiconductor substrate having an array region has a plurality of gaps so as to form discrete isolation structures and thereby implant source lines in the gaps of the semiconductor substrate. Since the source lines are not severed by the isolation structures, the required quantity of barrier pins not connected to the source line is greatly reduced, thereby reducing the space required for the barrier pins in the non-volatile memory.

公开(公告)号：US08012825B2

公开(公告)日：2011-09-06

申请号：US12350298

申请日：2009-01-08

Applicant: Yider Wu ,  Yung-Chung Lee ,  Yi-Hsiu Chen

Inventor： Yider Wu ,  Yung-Chung Lee ,  Yi-Hsiu Chen

IPC: H01L21/336

CPC classification number: H01L27/11521 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: In a method of manufacturing a double-implant NOR flash memory structure, a phosphorus ion implantation process is performed, so that a P-doped drain region is formed in a semiconductor substrate between two gate structures to overlap with a highly-doped drain (HDD) region and a lightly-doped drain (LDD) region. Therefore, the electric connection at a junction between the HDD region and the LDD region is enhanced and the carrier mobility in the memory is not lowered while the problems of short channel effect and punch-through of LDD region are solved.

Abstract translation: 在制造双注入NOR NOR闪存结构的方法中，执行磷离子注入工艺，使得在两个栅极结构之间的半导体衬底中形成P掺杂漏极区，以与高掺杂漏极（HDD ）区域和轻掺杂漏极（LDD）区域。 因此，解决了HDD区域和LDD区域之间的连接处的电连接，并且解决了存储器中的载流子迁移率，同时解决了LDD区域的短沟道效应和穿通问题。

公开(公告)号：US20100227447A1

公开(公告)日：2010-09-09

申请号：US12399124

申请日：2009-03-06

Applicant: Hung-Wei Chen ,  Yider Wu

Inventor： Hung-Wei Chen ,  Yider Wu

IPC: H01L21/8234

CPC classification number: H01L27/11519 ,  H01L29/40114

Abstract: A flash memory device manufacturing process includes the steps of providing a semiconductor substrate; forming two gate structures on the substrate; performing an ion implantation process to form two first source regions in the substrate at two lateral outer sides of the two gate structures; performing a further ion implantation process to form a first drain region in the substrate between the two gate structures; performing a pocket implantation process between the gate structures to form two doped regions in the substrate at two opposite sides of the first drain region; forming two facing L-shaped spacer walls between the two gate structures above the first drain region; performing an ion implantation process to form a second drain region beneath the first drain region, both of which having a steep junction profile compared to the first source regions; and forming a barrier plug above the first drain region.

Abstract translation: 闪存器件制造方法包括以下步骤：提供半导体衬底; 在基板上形成两个栅极结构; 执行离子注入工艺以在两个栅极结构的两个侧向外侧处在衬底中形成两个第一源极区域; 执行另外的离子注入工艺以在所述两个栅极结构之间的所述衬底中形成第一漏极区; 在所述栅极结构之间执行凹穴注入工艺，以在所述衬底中在所述第一漏极区的两个相对侧形成两个掺杂区域; 在所述第一漏极区域之上的所述两个栅极结构之间形成两个面对的L形间隔壁; 执行离子注入工艺以在所述第一漏极区域下方形成第二漏极区域，所述第二漏极区域与所述第一源极区域相比具有陡峭的接合轮廓; 以及在所述第一漏极区域上方形成阻挡塞。

公开(公告)号：US20100197108A1

公开(公告)日：2010-08-05

申请号：US12761460

申请日：2010-04-16

Applicant: Yider Wu

Inventor： Yider Wu

IPC: H01L21/28 ,  H01L21/762

CPC classification number: H01L29/78 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A non-volatile semiconductor manufacturing method comprises the steps of making element isolation/insulation films that partitions element-forming regions in a semiconductor substrate; stacking a floating gate on the semiconductor substrate via a first gate insulating film; stacking a second gate insulating film formed on the floating gate, and stacking a control gate formed on the floating gate via the second gate insulating film, and self-aligning source and drain diffusion area with the control gate. In the process of stacking a floating gate by partially etching a field oxide film in a select gate area, followed by floating gate formed in a element-forming region and select gate region, and followed by a chemical mechanical polish(CMP) process, both floating gate and select gate is hereby formed simultaneously. Thereby, when memory cells are miniaturized, the invention allows the process to be simple and reduce the defect density.

Abstract translation: 非易失性半导体制造方法包括以下步骤：制造在半导体衬底中分隔元件形成区域的元件隔离/绝缘膜; 通过第一栅极绝缘膜在半导体衬底上堆叠浮置栅极; 堆叠形成在浮置栅极上的第二栅极绝缘膜，并且通过第二栅极绝缘膜堆叠形成在浮置栅极上的控制栅极以及与控制栅极的自对准源极和漏极扩散区域。 在通过在选择栅极区域中局部蚀刻场氧化物膜的同时堆叠浮栅的过程中，随后是形成在元件形成区域中的浮栅并选择栅极区域，然后进行化学机械抛光（CMP）工艺， 浮动门和选择门同时形成。 因此，当存储单元小型化时，本发明允许该过程简单并减少缺陷密度。

公开(公告)号：US20070026675A1

公开(公告)日：2007-02-01

申请号：US11193409

申请日：2005-08-01

Applicant: Unsoon Kim ,  Angela Hui ,  Yider Wu ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita

Inventor： Unsoon Kim ,  Angela Hui ,  Yider Wu ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita

IPC: H01L21/302

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11531

Abstract: A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.

Abstract translation: 提供了一种用于形成存储器件的方法。 在衬底上形成氮化物层。 蚀刻氮化物层和衬底以形成沟槽。 在沟槽的相对侧上修整氮化物层，以加宽氮化物层内的沟槽。 沟槽填充有氧化物材料。 从存储器件剥离氮化物层，在沟槽上方形成台面。

公开(公告)号：US06509232B1

公开(公告)日：2003-01-21

申请号：US09969573

申请日：2001-10-01

Applicant: Unsoon Kim ,  Mark S. Chang ,  Yider Wu ,  Chi Chang ,  Angela Hui ,  Yu Sun

Inventor： Unsoon Kim ,  Mark S. Chang ,  Yider Wu ,  Chi Chang ,  Angela Hui ,  Yu Sun

IPC: H01L21336

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11536

Abstract: STI (shallow trench isolation) structures are formed for a flash memory device fabricated within an semiconductor substrate comprised of a core area having an array of core flash memory cells fabricated therein and comprised of a periphery area having logic circuitry fabricated therein. A first set of STI (shallow trench isolation) openings within the core area are etched through the semiconductor substrate, and a second set of STI (shallow trench isolation) openings within the periphery area are etched through the semiconductor substrate. A core active device area of the semiconductor substrate within the core area is surrounded by the first set of STI openings, and a periphery active device area of the semiconductor substrate within the periphery area is surrounded by the second set of STI openings. Dielectric liners are formed at sidewalls of the first and second sets of STI openings with reaction of the semiconductor substrate at the sidewalls of the STI openings such that top corners of the semiconductor substrate of the core and periphery active device areas adjacent the STI openings are rounded. A trench dielectric material is deposited to fill the STI openings. In addition, the top corners of the periphery active device area are exposed by etching portions of the sidewalls of the second set of STI structures in a dip-off etch. The exposed top corners of the periphery active device area are further rounded after additional thermal oxidation of the exposed top corners of the periphery active device area. The rounded corners of the core and periphery active device areas result in minimized leakage current through a flash memory cell fabricated within the core active device area and through a MOSFET fabricated within the periphery active device area.

Abstract translation: 形成STI（浅沟槽隔离）结构，用于制造在半导体衬底内的闪存器件，该半导体衬底由具有在其中制造的核心闪存单元阵列的核心区域组成，并由其中制造的逻辑电路的外围区域组成。 核心区域内的第一组STI（浅沟槽隔离）开口被蚀刻穿过半导体衬底，并且外围区域内的第二组STI（浅沟槽隔离）开口被蚀刻穿过半导体衬底。 核心区域内的半导体衬底的核心有源器件区域由第一组STI开口包围，并且周边区域内的半导体衬底的外围有源器件区域被第二组STI开口包围。 电介质衬垫通过半导体衬底在STI开口的侧壁处的反应而形成在第一和第二组STI开口的侧壁处，使得芯部的半导体衬底和邻近STI开口的周边有源器件区域的顶角是圆形的 。 沉积沟槽电介质材料以填充STI开口。 此外，通过在浸渍蚀刻中蚀刻第二组STI结构的侧壁的部分来暴露外围有源器件区域的顶角。 外围有源器件区域的暴露的顶角在外围有源器件区域的暴露顶角的额外的热氧化之后被进一步倒圆。 核心和外围有源器件区域的圆角导致通过在核心有源器件区域内制造的闪存单元和通过在外围有源器件区域内制造的MOSFET的最小化的漏电流。