公开(公告)号：US20100227447A1

公开(公告)日：2010-09-09

申请号：US12399124

申请日：2009-03-06

申请人： Hung-Wei Chen ,  Yider Wu

发明人： Hung-Wei Chen ,  Yider Wu

IPC分类号： H01L21/8234

CPC分类号： H01L27/11519 ,  H01L29/40114

摘要： A flash memory device manufacturing process includes the steps of providing a semiconductor substrate; forming two gate structures on the substrate; performing an ion implantation process to form two first source regions in the substrate at two lateral outer sides of the two gate structures; performing a further ion implantation process to form a first drain region in the substrate between the two gate structures; performing a pocket implantation process between the gate structures to form two doped regions in the substrate at two opposite sides of the first drain region; forming two facing L-shaped spacer walls between the two gate structures above the first drain region; performing an ion implantation process to form a second drain region beneath the first drain region, both of which having a steep junction profile compared to the first source regions; and forming a barrier plug above the first drain region.

摘要翻译： 闪存器件制造方法包括以下步骤：提供半导体衬底; 在基板上形成两个栅极结构; 执行离子注入工艺以在两个栅极结构的两个侧向外侧处在衬底中形成两个第一源极区域; 执行另外的离子注入工艺以在所述两个栅极结构之间的所述衬底中形成第一漏极区; 在所述栅极结构之间执行凹穴注入工艺，以在所述衬底中在所述第一漏极区的两个相对侧形成两个掺杂区域; 在所述第一漏极区域之上的所述两个栅极结构之间形成两个面对的L形间隔壁; 执行离子注入工艺以在所述第一漏极区域下方形成第二漏极区域，所述第二漏极区域与所述第一源极区域相比具有陡峭的接合轮廓; 以及在所述第一漏极区域上方形成阻挡塞。

公开(公告)号：US08476156B1

公开(公告)日：2013-07-02

申请号：US13338405

申请日：2011-12-28

申请人： Yider Wu ,  Hung-Wei Chen

发明人： Yider Wu ,  Hung-Wei Chen

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7881

摘要： In a manufacturing method of a flash memory structure with a stress area, a better stress effect can be achieved by controlling the manufacturing process of a tunneling oxide layer formed in a gate structure and contacted with a silicon substrate, so that an L-shaped spacer (or a first stress area) and a contact etch stop layer (or a second stress area) of each L-shaped spacer are formed between two gate structures and aligned towards each other to enhance the carrier mobility of the gate structure, so as to achieve the effects of improving a read current, obtaining the required read current by using a lower read voltage, reducing the possibility of having a stress-induced leakage current, and enhancing the data preservation of the flash memory.

摘要翻译： 在具有应力区域的闪存结构的制造方法中，通过控制形成在栅极结构中并与硅衬底接触的隧道氧化物层的制造工艺，可以获得更好的应力效应，使得L形间隔物 （或第一应力区域）和每个L形间隔物的接触蚀刻停止层（或第二应力区域）形成在两个栅极结构之间并且彼此对准以增强栅极结构的载流子迁移率，从而 实现改善读取电流的效果，通过使用较低的读取电压获得所需的读取电流，减少产生应力引起的漏电流的可能性，以及增强闪速存储器的数据保存。

公开(公告)号：US20100090256A1

公开(公告)日：2010-04-15

申请号：US12249152

申请日：2008-10-10

申请人： Hung-Wei Chen ,  Yider Wu

发明人： Hung-Wei Chen ,  Yider Wu

IPC分类号： H01L29/04

CPC分类号： H01L29/045 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/7843 ,  H01L29/7881

摘要： A semiconductor structure with stress regions includes a substrate defining a first and a second device zone; a first and a second stress region formed in each of the first and second device zones to yield stress different in level; and a barrier plug separating the two device zones from each other. Due to the stress yielded at the stress regions, increased carrier mobility and accordingly, increased reading current can be obtained, and a relatively lower reading voltage is needed to obtain initially required reading current. As a result, the probability of stress-induced leakage current (SILC) is reduced and the semiconductor memory structure may have enhanced data retention ability.

摘要翻译： 具有应力区域的半导体结构包括限定第一和第二器件区的衬底; 形成在所述第一和第二装置区域中的每一个中的第一和第二应力区域，以产生不同水平的应力; 以及将两个装置区彼此分开的阻挡塞。 由于在应力区产生的应力，载流子迁移率增加，因此可以获得增加的读取电流，并且需要相对较低的读取电压来获得最初需要的读取电流。 结果，应力诱发漏电流（SILC）的概率降低，并且半导体存储器结构可能具有增强的数据保留能力。

公开(公告)号：US20110230028A1

公开(公告)日：2011-09-22

申请号：US12728348

申请日：2010-03-22

申请人： Yider Wu ,  Hung-Wei Chen

发明人： Yider Wu ,  Hung-Wei Chen

IPC分类号： H01L21/8234

CPC分类号： H01L27/11521 ,  H01L27/11519

摘要： In a manufacturing method of a straight word line NOR flash memory array, a source line is implanted after the formation of a word line in the NOR type flash memory array is completed, and a discrete implant region is formed in the NOR type flash memory array and parallel to a component isolation structure, and each discrete implant region constitutes an electric connection with a low impedance between a source line and source contacts on the source line. With such discrete distribution, adjacent memory cells will not be short-circuited or failed even if a deviation of a mash occurs during the manufacturing process.

摘要翻译： 在直线NOR闪存阵列的制造方法中，在NOR型闪速存储器阵列中形成字线之后植入源极线，并且在NOR型闪存阵列中形成离散的注入区域 并且平行于部件隔离结构，并且每个离散注入区域构成源极线和源极线上的源极触点之间具有低阻抗的电连接。 通过这种离散分布，即使在制造过程中发生醪液的偏差，相邻的存储单元也不会短路或失效。

公开(公告)号：US08008692B2

公开(公告)日：2011-08-30

申请号：US12233486

申请日：2008-09-18

申请人： Hung-Wei Chen ,  Yider Wu

发明人： Hung-Wei Chen ,  Yider Wu

IPC分类号： H01L29/04

CPC分类号： H01L29/7881 ,  H01L29/42324 ,  H01L29/7843

摘要： A semiconductor memory structure with stress regions includes a substrate defining a first and a second device zone; a first and a second stress region formed in each of the first and second device zone to yield stress different in level; a barrier plug separating the two device zones from each other; and a plurality of oxide spacers being located between the first stress regions and the barrier plug while in direct contact with the first stress regions. Due to the stress yielded at the stress regions, increased carrier mobility and accordingly, increased reading current can be obtained, and only a relatively lower reading voltage is needed to obtain an initially required reading current. As a result, the probability of stress-induced leakage current is reduced to enhance the data retention ability.

摘要翻译： 具有应力区域的半导体存储器结构包括限定第一和第二器件区的衬底; 形成在第一和第二装置区域中的每一个中的第一和第二应力区域以产生不同水平的应力; 将两个装置区彼此分开的阻挡塞; 并且多个氧化物间隔物位于第一应力区域和阻挡塞之间，同时与第一应力区域直接接触。 由于在应力区产生的应力，载流子迁移率增加，因此可以获得增加的读取电流，并且仅需要相对较低的读取电压以获得最初需要的读取电流。 结果，减小了应力诱发漏电流的概率，提高了数据保留能力。

公开(公告)号：US20100065893A1

公开(公告)日：2010-03-18

申请号：US12233486

申请日：2008-09-18

申请人： Hung-Wei Chen ,  Yider Wu

发明人： Hung-Wei Chen ,  Yider Wu

IPC分类号： H01L29/04

CPC分类号： H01L29/7881 ,  H01L29/42324 ,  H01L29/7843

摘要： A semiconductor memory structure with stress regions includes a substrate defining a first and a second device zone; a first and a second stress region formed in each of the first and second device zone to yield stress different in level; a barrier plug separating the two device zones from each other; and a plurality of oxide spacers being located between the first stress regions and the barrier plug while in direct contact with the first stress regions. Due to the stress yielded at the stress regions, increased carrier mobility and accordingly, increased reading current can be obtained, and only a relatively lower reading voltage is needed to obtain an initially required reading current. As a result, the probability of stress-induced leakage current is reduced to enhance the data retention ability.

摘要翻译： 具有应力区域的半导体存储器结构包括限定第一和第二器件区的衬底; 形成在第一和第二装置区域中的每一个中的第一和第二应力区域以产生不同水平的应力; 将两个装置区彼此分开的阻挡塞; 并且多个氧化物间隔物位于第一应力区域和阻挡塞之间，同时与第一应力区域直接接触。 由于在应力区产生的应力，载流子迁移率增加，因此可以获得增加的读取电流，并且仅需要相对较低的读取电压以获得最初需要的读取电流。 结果，减小了应力诱发漏电流的概率，提高了数据保留能力。

公开(公告)号：US20090140351A1

公开(公告)日：2009-06-04

申请号：US11948823

申请日：2007-11-30

申请人： Hong-Nien Lin ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

发明人： Hong-Nien Lin ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

IPC分类号： H01L29/78

CPC分类号： H01L29/6656 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming a slim spacer on sidewalls of the gate dielectric and the gate electrode; forming a silicon carbon (SiC) region adjacent the slim spacer; forming a deep source/drain region comprising at least a portion of the silicon carbon region; blanket forming a metal layer, wherein a first interface between the metal layer and the deep source/drain is higher than a second interface between the gate dielectric and the semiconductor substrate; and annealing the semiconductor device to form a silicide region. Preferably, a horizontal spacing between an inner edge of the silicide region and a respective edge of the gate electrode is preferably less than about 150 Å.

摘要翻译： 一种形成半导体器件的方法包括提供半导体衬底; 在所述半导体衬底上形成栅极电介质; 在所述栅极电介质上形成栅电极; 在所述栅极电介质和所述栅电极的侧壁上形成细长间隔物; 形成邻近细长间隔物的硅碳（SiC）区域; 形成包含所述硅碳区域的至少一部分的深源极/漏极区域; 毯形成金属层，其中金属层和深源极/漏极之间的第一界面高于栅极电介质和半导体衬底之间的第二界面; 并对半导体器件进行退火以形成硅化物区域。 优选地，硅化物区域的内边缘和栅电极的相应边缘之间的水平间隔优选小于约150埃。

公开(公告)号：US07538351B2

公开(公告)日：2009-05-26

申请号：US11089405

申请日：2005-03-23

申请人： Hung-Wei Chen ,  Hsun-Chih Tsao ,  Kuang-Hsin Chen ,  Di-Hong Lee

发明人： Hung-Wei Chen ,  Hsun-Chih Tsao ,  Kuang-Hsin Chen ,  Di-Hong Lee

IPC分类号： H01L29/10

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0251 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7843 ,  H01L29/7851 ,  H01L29/7854

摘要： A semiconductor device and method for forming the same including improved electrostatic discharge protection for advanced semiconductor devices, the semiconductor device including providing semiconductor substrate having a pre-selected surface orientation and crystal direction; an insulator layer overlying the semiconductor substrate; a first semiconductor active region overlying the insulator layer having a first surface orientation selected from the group consisting of and ; a second semiconductor active region extending through a thickness portion of the insulator layer having a second surface orientation selected from the group consisting of and different from the first surface orientation; wherein MOS devices including a first MOS device of a first conduction type is disposed on the first semiconductor active region and a second MOS device of a second conduction type is disposed on the second semiconductor active region.

摘要翻译： 一种半导体器件及其制造方法，包括提供先进半导体器件的改进的静电放电保护，所述半导体器件包括提供具有预选择的表面取向和晶体方向的半导体衬底; 覆盖半导体衬底的绝缘体层; 覆盖绝缘体层的第一半导体有源区具有选自<100>和<110>的第一表面取向; 延伸穿过绝缘体层的厚度部分的第二半导体有源区，其具有选自与第一表面取向不同的<110>和<100>的第二表面取向; 其中包括第一导电类型的第一MOS器件的MOS器件设置在第一半导体有源区上，并且第二导电类型的第二MOS器件设置在第二半导体有源区上。

公开(公告)号：US20090117695A1

公开(公告)日：2009-05-07

申请号：US12260674

申请日：2008-10-29

申请人： Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

发明人： Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

IPC分类号： H01L21/8249

CPC分类号： H01L21/8249 ,  H01L21/823807 ,  H01L27/0623 ,  H01L29/7843

摘要： A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT.

摘要翻译： 提供了通过机械单轴应变增强性能的BiCMOS器件。 本发明的第一实施例包括形成在衬底的不同区域上的NMOS晶体管，PMOS晶体管和双极晶体管。 具有拉伸应力的第一接触蚀刻停止层形成在NMOS晶体管上，并且在PMOS晶体管和双极晶体管上形成具有压应力的第二接触蚀刻停止层，从而允许每个器件的增强。 除了应力接触蚀刻停止层之外，另一实施例还包括PMOS晶体管和NMOS晶体管中的应变通道区域以及BJT中的应变基极。

公开(公告)号：US20070103568A1

公开(公告)日：2007-05-10

申请号：US11415255

申请日：2006-05-02

申请人： Hung-Wei Chen

发明人： Hung-Wei Chen

IPC分类号： H04N5/262

CPC分类号： H04N5/2628

摘要： A method of enlarging an image by interpolation means and a related digital camera are disclosed. The method comprises: dividing an original image into a plurality of divided sections; defining a first divided section selected from the plurality of divided sections; defining a second divided section from the divided sections adjacent thereto and continuing until defining a final divided section; enlarging the first divided section by a first specific multiplier and zooming out by a second specific multiplier by using the interpolation means to form a first processed section, and continuing until a final processed section is formed. The first processed section to the final processed section thereby form an enlarged image.

摘要翻译： 公开了一种通过插值装置和相关数字照相机放大图像的方法。 该方法包括：将原始图像划分成多个划分的部分; 限定从所述多个分割部分中选择的第一分割部分; 从与其相邻的分割部分定义第二分割部分，并且继续直到定义最终分割部分; 通过第一特定乘法器放大第一分割区域并通过使用内插装置来缩放第二特定乘数，以形成第一处理部分，并且继续直到形成最终处理部分。 第一处理部分到最终处理部分，从而形成放大图像。