公开(公告)号：US20160377991A1

公开(公告)日：2016-12-29

申请号：US14865044

申请日：2015-09-25

申请人： Yiming Zhu ,  Lijun Chen ,  Peng Wu ,  Jun Zhu

发明人： Yiming Zhu ,  Lijun Chen ,  Peng Wu ,  Jun Zhu

IPC分类号： G03F7/20

CPC分类号： G03F7/70633

摘要： The present invention provides a method for solving the need for layer management with double-layer overlay accuracy control, a calibration mark structure which realizes the method and a measurement system with the calibration mark structure. The method modifies the layout of the overlay calibration marks such that overlay information of two layers is contained in one combined calibration mark, has realized the overlay accuracy data collection for the two previous layers in the current layer by one-time measurement, and can treat the overlay accuracies of the two layers as different control accuracies. Thus, the method can complete the automatic feedback optimization of the overlay accuracy compensation, is simple and easy, and can better help the enterprises for production quality assurance and cost control.

摘要翻译： 本发明提供一种用于解决对具有双层覆盖精度控制的层管理的需要的方法，实现该方法的校准标记结构和具有校准标记结构的测量系统。 该方法修改叠加校准标记的布局，使得两层叠加信息包含在一个组合校准标记中，通过一次测量实现了当前层中两个先前层的叠加精度数据采集，并可以处理 两层的覆盖精度作为不同的控制精度。 因此，该方法可以完成覆盖精度补偿的自动反馈优化，简单易行，可以更好地帮助企业进行生产质量保证和成本控制。

公开(公告)号：US20070241384A1

公开(公告)日：2007-10-18

申请号：US11404194

申请日：2006-04-14

申请人： Yiming Zhu

发明人： Yiming Zhu

IPC分类号： H01L29/76

CPC分类号： H01L29/7883 ,  H01L29/42324

摘要： The present invention provides methods and apparatuses for a non-volatile semiconductor memory device. A non-volatile semiconductor memory device having multiple layers to provide a source, a drain, and a floating gate, comprising a plurality of metal layers to provide interconnects to the non-volatile memory wherein at least two of the plurality of metal areas on one or more layers are configured to provide a capacitor having a capacitance that is capacitively coupled to the floating gate.

摘要翻译： 本发明提供了一种用于非易失性半导体存储器件的方法和装置。 一种具有多个层以提供源极，漏极和浮置栅极的非易失性半导体存储器件，包括多个金属层以提供与非易失性存储器的互连，其中多个金属区域中的至少两个在一个 或更多层被配置为提供具有电容耦合到浮动栅极的电容的电容器。

公开(公告)号：US20050226079A1

公开(公告)日：2005-10-13

申请号：US10928504

申请日：2004-08-26

申请人： Yiming Zhu ,  Qingming Shu

发明人： Yiming Zhu ,  Qingming Shu

IPC分类号： G11C7/00 ,  G11C8/16 ,  G11C11/405 ,  G11C11/406

CPC分类号： G11C11/40603 ,  G11C8/16 ,  G11C11/405 ,  G11C11/406 ,  G11C11/40615

摘要： Memory methods and apparatuses providing for refresh and bandwidth enhancements for a dual-port memory array (e.g. a DRAM memory array) with balanced read and write timing specifications are disclosed. A port allocation for dual-port memory cell is adopted such that one port is assigned and shared for both read and refresh and the other port is assigned for write only. Double bandwidth is achieved by overlapping simultaneous read or refresh and write port access during the same cycle. No external refresh command is required and external accesses (reads and writes) are not interrupted or delayed under any circumstance. A high-speed SRAM compatible device can be fabricated from a dual-port DRAM or 3-Transistor cells or 2-Transistors and 1 capacitor cells. The preferred embodiments include a multi-bank dual-port memory array and a look-up-table logic which records the accessed word address and generates hit logic and idle cycles when a refresh stall is asserted by a refresh-jammed bank. A dual-port memory data lodge which temporarily detours the data flow is provided to store the data flow and to allow for refresh to occur in the refresh-jammed bank. Each of dual-port DRAM banks has its independent read, write and refresh decoder control. Therefore, simultaneous refresh and read-write operations are allowed in different banks. The size of data lodge is determined by guaranteeing that the refresh operations can be executed without pausing ongoing indefinite read and write operations.

摘要翻译： 公开了具有平衡的读和写定时规范的双端口存储器阵列（例如，DRAM存储器阵列）提供刷新和带宽增强的存储器方法和装置。 采用双端口存储单元的端口分配，以便为读取和刷新分配一个端口并共享一个端口，另一个端口被分配用于写入。 通过在同一周期内重叠同时读取或刷新和写入端口访问来实现双重带宽。 不需要外部刷新命令，并且在任何情况下外部访问（读取和写入）都不会中断或延迟。 高速SRAM兼容器件可以由双端口DRAM或3晶体管单元或2晶体管和1个电容器单元制造。 优选实施例包括多存储双端口存储器阵列和查找表逻辑，其记录所访问的字地址，并且当由刷新卡块组建立刷新停顿时产生命中逻辑和空闲周期。 提供临时绕行数据流的双端口存储器数据仓，以存储数据流并允许在刷新卡块中进行刷新。 每个双端口DRAM组具有独立的读，写和刷新解码器控制。 因此，可以在不同的银行中同时进行刷新和读写操作。 通过保证可以执行刷新操作而不停止持续不定的读写操作来确定数据仓库的大小。

公开(公告)号：US20080315268A1

公开(公告)日：2008-12-25

申请号：US11766763

申请日：2007-06-21

申请人： Yiming Zhu

发明人： Yiming Zhu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/823892 ,  H01L21/823878 ,  H01L27/1052

摘要： The present invention discloses semiconductor devices that can be manufactured utilizing standard process of manufacturing and that can hold information. In accordance with a presently preferred embodiment of the present invention, one or more semiconductor devices can be formed in a well on a substrate where isolation trenches surround one or more devices to create storage regions (floating wells) that is capable of holding a charge. Depending on the charge in the storage region (floating well), it can represent information. The semiconductor devices of the present invention can be manufactured using the standard process of manufacturing (bulk cmos processing).

摘要翻译： 本发明公开了可以利用标准的制造工艺制造并可以保存信息的半导体器件。 根据本发明的当前优选实施例，可以在衬底上的阱中形成一个或多个半导体器件，其中隔离沟槽围绕一个或多个器件以产生能够保持电荷的存储区域（浮动阱）。 取决于存储区域（浮动井）中的电荷，它可以表示信息。 本发明的半导体器件可以使用标准制造工艺（批量cmos处理）来制造。

公开(公告)号：US07808055B2

公开(公告)日：2010-10-05

申请号：US11766763

申请日：2007-06-21

申请人： Yiming Zhu

发明人： Yiming Zhu

IPC分类号： H01L29/06

CPC分类号： H01L21/823892 ,  H01L21/823878 ,  H01L27/1052

摘要： The present invention discloses semiconductor devices that can be manufactured utilizing standard process of manufacturing and that can hold information. In accordance with a presently preferred embodiment of the present invention, one or more semiconductor devices can be formed in a well on a substrate where isolation trenches surround one or more devices to create storage regions (floating wells) that is capable of holding a charge. Depending on the charge in the storage region (floating well), it can represent information. The semiconductor devices of the present invention can be manufactured using the standard process of manufacturing (bulk cmos processing).

摘要翻译： 本发明公开了可以利用标准的制造工艺制造并可以保存信息的半导体器件。 根据本发明的当前优选实施例，可以在衬底上的阱中形成一个或多个半导体器件，其中隔离沟槽围绕一个或多个器件以产生能够保持电荷的存储区域（浮动阱）。 取决于存储区域（浮动井）中的电荷，它可以表示信息。 本发明的半导体器件可以使用标准制造工艺（批量cmos处理）来制造。