摘要:
Embodiments of compact micro-electro-mechanical systems (MEMS) devices are provided, as are embodiments of methods for fabricating MEMS devices. In one embodiment, the MEMS device includes a substrate, a movable structure resiliently coupled to the substrate, and an anchored structure fixedly coupled to the substrate. The movable structure includes a first plurality of movable fingers, and a second plurality of movable fingers electrically isolated from and interspersed with the first plurality of movable fingers. The anchored structure includes fixed fingers interspersed with first and second pluralities of movable fingers in a capacitor-forming relationship. First and second interconnects are electrically coupled to the first and second pluralities of movable fingers, respectively.
摘要:
Embodiments of compact micro-electro-mechanical systems (MEMS) devices are provided, as are embodiments of methods for fabricating MEMS devices. In one embodiment, the MEMS device includes a substrate, a movable structure resiliently coupled to the substrate, and an anchored structure fixedly coupled to the substrate. The movable structure includes a first plurality of movable fingers, and a second plurality of movable fingers electrically isolated from and interspersed with the first plurality of movable fingers. The anchored structure includes fixed fingers interspersed with first and second pluralities of movable fingers in a capacitor-forming relationship. First and second interconnects are electrically coupled to the first and second pluralities of movable fingers, respectively.
摘要:
A capacitance-to-voltage interface circuit includes a capacitive sensing circuit, an amplification circuit adapted for selective coupling to the capacitive sensing circuit, a capacitor bank comprising a plurality of binary-weighted capacitors, and a switching architecture associated with the capacitive sensing circuit, the amplification circuit, and the capacitor bank. The switching architecture reconfigures the capacitance-to-voltage interface circuit for operation in a plurality of different phases, including an amplification phase and an analog-to-digital conversion phase. During the amplification phase, the capacitor bank is utilized for offsetting capacitance of the amplification circuit. During the analog-to-digital conversion phase, the capacitor bank is utilized in a successive approximation register.
摘要:
A MEMS sensor packaged with an integrated circuit includes switches and control circuitry. In a test mode, the control circuitry causes the switches to turn off and on such that the first and second capacitance of the MEMS sensor can be monitored individually. During a normal mode of operation, the switches are maintained such that the MEMS sensor packaged with the integrated circuit operates to produce a filtered and trimmed output reflecting the sensed phenomena.
摘要:
A capacitance-to-voltage interface circuit is utilized to obtain a voltage corresponding to a detected capacitance differential, which may be associated with the operation of a capacitive sensing cell. The interface circuit includes a capacitive sensing cell, an operational amplifier adapted for selective coupling to the capacitive sensing cell, a feedback capacitor for the operational amplifier, a load capacitor for the operational amplifier, and a switching architecture associated with the capacitive sensing cell, the operational amplifier, the feedback capacitor, and the load capacitor. During use, the switching architecture reconfigures the capacitance-to-voltage interface circuit for operation in a plurality of different phases. The different operational phases enable the single operational amplifier to be used for both capacitance-to-voltage conversion and voltage amplification.
摘要:
A capacitance-to-voltage interface circuit is utilized to obtain a voltage corresponding to a detected capacitance differential, which may be associated with the operation of a capacitive sensing cell. The interface circuit includes a capacitive sensing cell, an operational amplifier adapted for selective coupling to the capacitive sensing cell, a feedback capacitor for the operational amplifier, a load capacitor for the operational amplifier, and a switching architecture associated with the capacitive sensing cell, the operational amplifier, the feedback capacitor, and the load capacitor. During use, the switching architecture reconfigures the capacitance-to-voltage interface circuit for operation in a plurality of different phases. The different operational phases enable the single operational amplifier to be used for both capacitance-to-voltage conversion and voltage amplification.
摘要:
A capacitance-to-voltage interface circuit is utilized to obtain a voltage corresponding to a detected capacitance differential, which may be associated with the operation of a capacitive sensing cell. The interface circuit includes a capacitive sensing cell, an operational amplifier adapted for selective coupling to the capacitive sensing cell, a feedback capacitor for the operational amplifier, a load capacitor for the operational amplifier, and a switching architecture associated with the capacitive sensing cell, the operational amplifier, the feedback capacitor, and the load capacitor. During use, the switching architecture reconfigures the capacitance-to-voltage interface circuit for operation in a plurality of different phases. The different operational phases enable the single operational amplifier to be used for both capacitance-to-voltage conversion and voltage amplification.
摘要:
A capacitance-to-voltage interface circuit is utilized to obtain a voltage corresponding to a detected capacitance differential, which may be associated with the operation of a capacitive sensing cell. The interface circuit includes a capacitive sensing cell, an operational amplifier adapted for selective coupling to the capacitive sensing cell, a feedback capacitor for the operational amplifier, a load capacitor for the operational amplifier, and a switching architecture associated with the capacitive sensing cell, the operational amplifier, the feedback capacitor, and the load capacitor. During use, the switching architecture reconfigures the capacitance-to-voltage interface circuit for operation in a plurality of different phases. The different operational phases enable the single operational amplifier to be used for both capacitance-to-voltage conversion and voltage amplification.
摘要:
The analog-to-digital converter provided herein includes a capacitor bank comprising a plurality of binary-weighted capacitors, an operational amplifier having an inverting input node, a noninverting input node coupled to analog ground, and an output node, a reset switch, and an input switch. The reset switch is located between the capacitor bank and the operational amplifier, and it selectively couples the capacitor bank to the inverting input node. The input switch has its common terminal coupled to the capacitor bank, and the input switch selectively couples the capacitor bank to either an analog input voltage, a floating terminal, or analog ground. The capacitor bank includes N binary-weighted capacitors and one balancing capacitor that has a unit capacitance. During operation, the analog-to-digital converter generates an N-bit digital output and one polarity bit from the analog input voltage.
摘要:
The analog-to-digital converter provided herein includes a capacitor bank comprising a plurality of binary-weighted capacitors, an operational amplifier having an inverting input node, a noninverting input node coupled to analog ground, and an output node, a reset switch, and an input switch. The reset switch is located between the capacitor bank and the operational amplifier, and it selectively couples the capacitor bank to the inverting input node. The input switch has its common terminal coupled to the capacitor bank, and the input switch selectively couples the capacitor bank to either an analog input voltage, a floating terminal, or analog ground. The capacitor bank includes N binary-weighted capacitors and one balacing capacitor that has a unit capacitance. During operation, the analog-to-digital converter generates an N-bit digital output and one polarity bit from the analog input voltage.