公开(公告)号：US08134384B2

公开(公告)日：2012-03-13

申请号：US12514005

申请日：2006-11-08

申请人： Yoav Weizman ,  Yehim-Haim Fefer ,  Sergey Sofer

发明人： Yoav Weizman ,  Yehim-Haim Fefer ,  Sergey Sofer

IPC分类号： G01R31/34

CPC分类号： G01R31/3004 ,  G01R29/26 ,  G01R31/31721

摘要： A method for testing a noise immunity of an integrated circuit; the method includes: determining a value of a power supply noise regardless of a relationship between the power supply noise value and a phase sensitive signal edge position resulting from an introduction of the power supply noise; receiving, by the integrated circuit, a phase sensitive signal; introducing jitter to the phase sensitive signal by a circuit adapted to generate a substantially continuous range of power supply noise such as to alter edges position of the phase sensitive signal; providing the jittered phase sensitive signal to at least one tested component of the integrated circuit; and evaluating at least one output signal generated by the at least tested component to determine the noise immunity of the integrated circuit.

摘要翻译： 一种用于测试集成电路的抗噪声的方法; 该方法包括：确定电源噪声的值，而不管电源噪声值与由引入电源噪声导致的相敏信号边沿位置之间的关系如何; 通过集成电路接收相敏信号; 通过适于产生基本连续的电源噪声范围的电路将抖动引入相位敏感信号，例如改变相位敏感信号的边沿位置; 向所述集成电路的至少一个测试部件提供抖动的相位敏感信号; 以及评估由所述至少被测试的部件产生的至少一个输出信号，以确定所述集成电路的抗噪声性。

公开(公告)号：US20100001755A1

公开(公告)日：2010-01-07

申请号：US12514005

申请日：2006-11-08

申请人： Yoav Weizman ,  Yehim-Haim Fefer ,  Sergey Sofer

发明人： Yoav Weizman ,  Yehim-Haim Fefer ,  Sergey Sofer

IPC分类号： G01R31/26

CPC分类号： G01R31/3004 ,  G01R29/26 ,  G01R31/31721

摘要： A method for testing a noise immunity of an integrated circuit; the method includes: determining a value of a power supply noise regardless of a relationship between the power supply noise value and a phase sensitive signal edge position resulting from an introduction of the power supply noise; receiving, by the integrated circuit, a phase sensitive signal; introducing jitter to the phase sensitive signal by a circuit adapted to generate a substantially continuous range of power supply noise such as to alter edges position of the phase sensitive signal; providing the jittered phase sensitive signal to at least one tested component of the integrated circuit; and evaluating at least one output signal generated by the at least tested component to determine the noise immunity of the integrated circuit.

摘要翻译： 一种用于测试集成电路的抗噪声的方法; 该方法包括：确定电源噪声的值，而不管电源噪声值与由引入电源噪声导致的相敏信号边沿位置之间的关系如何; 通过集成电路接收相敏信号; 通过适于产生基本连续的电源噪声范围的电路将抖动引入相位敏感信号，例如改变相位敏感信号的边沿位置; 向所述集成电路的至少一个测试部件提供抖动的相位敏感信号; 以及评估由所述至少被测试的部件产生的至少一个输出信号，以确定所述集成电路的抗噪声性。

公开(公告)号：US09671456B2

公开(公告)日：2017-06-06

申请号：US14395707

申请日：2012-04-23

申请人： Yoav Weizman ,  Jacob Fridburg ,  Shai Shperber

发明人： Yoav Weizman ,  Jacob Fridburg ,  Shai Shperber

IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/308 ,  H01L21/66

CPC分类号： G01R31/2882 ,  G01R31/308 ,  G01R31/31725 ,  H01L22/12 ,  H01L22/20 ,  H01L22/34

摘要： A semiconductor device arrangement comprising a functional circuit comprising a plurality of timing components and a reference module comprising a plurality of reference components is described. Each reference component comprises a reference timing component corresponding to a timing component of the plurality of timing components and a controllable timing component. The controllable timing component is arranged to provide a delay in dependence on an applied light stimulus. A method of analyzing a performance of a functional circuit on a semiconductor device is also described. A device analysis system for analyzing a functional circuit comprising a plurality of timing components is also described.

公开(公告)号：US08368383B2

公开(公告)日：2013-02-05

申请号：US12522034

申请日：2007-01-05

申请人： Yefim-Haim Fefer ,  Mikhail Bourgart ,  Segey Sofer ,  Yoav Weizman

发明人： Yefim-Haim Fefer ,  Mikhail Bourgart ,  Segey Sofer ,  Yoav Weizman

IPC分类号： H03L7/06 ,  H03K3/00 ,  G01R31/28

CPC分类号： G01R31/3016 ,  G01R31/2882

摘要： A device and a method for testing a variable digital delay line that includes multiple taps. The method includes providing, an input signal to the variable digital delay line and finding, for each tap out of a group of tested taps of the variable digital delay line, a variable delay unit configuration that provides a delay that is closest to a delay introduced by the tap; wherein the variable digital delay line and the variable delay unit belong to the same integrated circuit.

摘要翻译： 一种用于测试包括多个抽头的可变数字延迟线的装置和方法。 该方法包括向可变数字延迟线提供输入信号，并针对可变数字延迟线的测试抽头组中的每个抽头找出可变延迟单元配置，其提供最接近所引入的延迟的延迟 由水龙头 其中可变数字延迟线和可变延迟单元属于同一集成电路。

公开(公告)号：US20150015240A1

公开(公告)日：2015-01-15

申请号：US14380738

申请日：2012-02-27

申请人： Anton Rozen ,  Leonid Fleshel ,  Michael Priel ,  Yoav Weizman

发明人： Anton Rozen ,  Leonid Fleshel ,  Michael Priel ,  Yoav Weizman

IPC分类号： G01N21/66 ,  G01R15/24

CPC分类号： G01N21/66 ,  G01R15/24 ,  G01R31/311

摘要： A method of detecting irregular high current flow within an integrated circuit (IC) device is described. The method comprises obtaining infrared (IR) emission information for the IC device, identifying at least one functional component within the IC device comprising a high current flow, based at least partly on the obtained IR emission information, obtaining IR emission information for at least one reference component within the IC device, and determining whether the high current flow of the at least one functional component comprises an irregular high current flow based at least partly on a comparison of respective IR emission information for the at least one functional component and the at least one reference component.

摘要翻译： 描述了在集成电路（IC）装置内检测不规则高电流的方法。 该方法包括：至少部分地基于所获得的IR发射信息，获得IC器件的红外（IR）发射信息，识别包括高电流的IC器件内的至少一个功能部件，获得至少一个 参考部件，以及至少部分地基于用于至少一个功能部件的至少一个功能部件的相应IR发射信息的比较来确定所述至少一个功能部件的高电流是否包括不规则高电流 一个参考组件。

公开(公告)号：US20100072979A1

公开(公告)日：2010-03-25

申请号：US12522034

申请日：2007-01-05

申请人： Yefim-Haim Fefer ,  Mikhail Bourgart ,  Segey Sofer ,  Yoav Weizman

发明人： Yefim-Haim Fefer ,  Mikhail Bourgart ,  Segey Sofer ,  Yoav Weizman

IPC分类号： G01R25/00

CPC分类号： G01R31/3016 ,  G01R31/2882

摘要： A device and a method for testing a variable digital delay line that includes multiple taps. The method includes providing, an input signal to the variable digital delay line and finding, for each tap out of a group of tested taps of the variable digital delay line, a variable delay unit configuration that provides a delay that is closest to a delay introduced by the tap; wherein the variable digital delay line and the variable delay unit belong to the same integrated circuit.

摘要翻译： 一种用于测试包括多个抽头的可变数字延迟线的装置和方法。 该方法包括向可变数字延迟线提供输入信号，并针对可变数字延迟线的测试抽头组中的每个抽头找出可变延迟单元配置，其提供最接近所引入的延迟的延迟 由水龙头 其中可变数字延迟线和可变延迟单元属于同一集成电路。

公开(公告)号：US07151387B2

公开(公告)日：2006-12-19

申请号：US10672487

申请日：2003-09-26

申请人： Yoav Weizman ,  Shai Shperber ,  Ezra Baruch

发明人： Yoav Weizman ,  Shai Shperber ,  Ezra Baruch

IPC分类号： G01R31/02

CPC分类号： H01L22/34 ,  G01R31/2884 ,  G01R31/30 ,  G01R31/311

摘要： A system (5) for testing and failure analysis of an integrated circuit (10) is provided using failure analysis tools (40, 50, 60). An analysis module (30) having a number of submodule test structures is incorporated into the integrated circuit design. The test structures are chosen in dependence upon the failure analysis tools (40, 50, 60) to be used. The rest of the integrated circuit contains function modules (20) arranged to provide normal operating functions. By analysing the submodule test structures of the analysis module (30) using the failure analysis tools (40, 50, 60), physical parameters of the integrated circuit (10) are obtained and used in subsequent testing of the function modules (20) by the failure analysis tools (40, 50, 60), thus simplifying the testing of the integrated circuit (10) and reducing the time taken to perform a failure analysis procedure.

摘要翻译： 使用故障分析工具（40,50,60）提供用于集成电路（10）的测试和故障分析的系统（5）。 具有多个子模块测试结构的分析模块（30）被集成到集成电路设计中。 测试结构根据要使用的故障分析工具（40,50,60）进行选择。 集成电路的其余部分包含布置成提供正常操作功能的功能模块（20）。 通过使用故障分析工具（40,50,60）分析分析模块（30）的子模块测试结构，获得集成电路（10）的物理参数，并在功能模块（20）的后续测试中使用 故障分析工具（40,50,60），从而简化了集成电路（10）的测试并减少了执行故障分析过程所花费的时间。

公开(公告)号：US20120051398A1

公开(公告)日：2012-03-01

申请号：US13291252

申请日：2011-11-08

申请人： Yoav Weizman ,  Lior Aviv ,  Shai Shperber

发明人： Yoav Weizman ,  Lior Aviv ,  Shai Shperber

IPC分类号： G01K7/01

CPC分类号： G01K7/34 ,  G01K7/346

摘要： A method for evaluating temperature is disclosed. The method includes setting a configuration of a configurable delay line out of multiple possible configurations, and delaying a first input signal by a temperature sensitive delay line, delaying a second input signal by the configurable delay line. The configurable delay line is less sensitive to temperature than the temperature sensitive delay line. The method also includes detecting, by a phase detector, a delay difference between a delay introduced by the temperature sensitive delay line and a delay introduced by the configurable delay line, repeating the setting, delaying of the first input signal, delaying of the second input signal and detecting, until the delay difference is below a threshold, and evaluating the temperature of the temperature sensitive delay line in response to a configuration of the configurable delay line that results in the delay difference that is below the threshold.

摘要翻译： 公开了一种评估温度的方法。 该方法包括设置多个可能配置中的可配置延迟线的配置，以及通过温度敏感延迟线延迟第一输入信号，通过可配置的延迟线延迟第二输入信号。 可配置的延迟线比温度敏感延迟线对温度敏感度较低。 该方法还包括由相位检测器检测由温度敏感延迟线引入的延迟与由可配置延迟线引入的延迟之间的延迟差，重复该设置，延迟第一输入信号，延迟第二输入 信号和检测，直到延迟差低于阈值，并且响应于导致低于阈值的延迟差的可配置延迟线的配置来评估温度敏感延迟线的温度。

公开(公告)号：US08070357B2

公开(公告)日：2011-12-06

申请号：US12179839

申请日：2008-07-25

申请人： Yoav Weizman ,  Lior Aviv ,  Shai Shperber

发明人： Yoav Weizman ,  Lior Aviv ,  Shai Shperber

IPC分类号： G01K7/00

CPC分类号： G01K7/34 ,  G01K7/346

摘要： A device having temperature evaluating capabilities, the device includes: (i) a temperature sensitive delay line that comprises multiple first type NMOS transistors and first type PMOS transistors; (ii) an configurable delay line that comprises second type NMOS transistors and second type PMOS transistors; wherein a process condition sensitivity of first type NMOS transistors and first type PMOS transistors substantially equals a process condition sensitivity of the second type NMOS transistors and second type PMOS transistors; wherein the configurable delay line is less sensitive to temperature than the temperature sensitive delay line; (iii) a phase detector, coupled to an output of the temperature sensitive delay line and to an output of the adjustable delay line, the phase detector is adapted to determine a difference between a delay introduced by the temperature sensitive delay line and a delay introduced by the adjustable delay line; and (iv) a controller, adapted to: (a) find a configuration of the configurable delay line that introduces a delay that substantially equals a delay introduced by the temperature sensitive delay line; and (b) determine a temperature of the temperature sensitive delay line in response to the found configuration.

摘要翻译： 一种具有温度评估能力的装置，该装置包括：（i）包括多个第一类型NMOS晶体管和第一类型PMOS晶体管的温度敏感延迟线; （ii）包括第二类型NMOS晶体管和第二类型PMOS晶体管的可配置延迟线; 其中第一型NMOS晶体管和第一型PMOS晶体管的工艺条件灵敏度基本上等于第二类型NMOS晶体管和第二类型PMOS晶体管的工艺条件灵敏度; 其中所述可配置延迟线对温度比所述温度敏感延迟线更不敏感; （iii）相位检测器，耦合到温度敏感延迟线的输出和可调延迟线的输出，相位检测器适于确定由温度敏感延迟线引入的延迟与引入的延迟之间的差 通过可调延迟线; 以及（iv）控制器，适于：（a）找到所述可配置延迟线的配置，其引入基本上等于由所述温度敏感延迟线引入的延迟的延迟; 和（b）响应于找到的配置来确定温度敏感延迟线的温度。

公开(公告)号：US09606064B2

公开(公告)日：2017-03-28

申请号：US14380738

申请日：2012-02-27

申请人： Anton Rozen ,  Leonid Fleshel ,  Michael Priel ,  Yoav Weizman

发明人： Anton Rozen ,  Leonid Fleshel ,  Michael Priel ,  Yoav Weizman

IPC分类号： G01N21/66 ,  G01R15/24 ,  G01R31/311

CPC分类号： G01N21/66 ,  G01R15/24 ,  G01R31/311

摘要： A method of detecting irregular high current flow within an integrated circuit (IC) device is described. The method comprises obtaining infrared (IR) emission information for the IC device, identifying at least one functional component within the IC device comprising a high current flow, based at least partly on the obtained IR emission information, obtaining IR emission information for at least one reference component within the IC device, and determining whether the high current flow of the at least one functional component comprises an irregular high current flow based at least partly on a comparison of respective IR emission information for the at least one functional component and the at least one reference component.